Suppose we have a byte-addressable memory of 20 bytes, built using 4 modules. Draw diagrams showing the distribution of addresses within each module, if we are using (a) high order interleaving, and (b) low-order interleaving.
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Suppose we have a byte-addressable memory of 20 bytes, built using 4 modules. Draw
diagrams showing the distribution of addresses within each module, if we are using (a) high
order interleaving, and (b) low-order interleaving.
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- Most Intel CPUs use the __________, in which each memory address is represented by two integers.Suppose we have a 64Kbyte byte-addressable memory that is 16-way low-order interleaved. What is the size of the memory address module number field? Explain why.Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) What is the format of a memory address as seen by cache; that is, what are the sizes of the tag and offset fields?
- Consider a memory implemented for 8086 microprocessor Draw the memory block diagram. Determine the values for A0 , /BHE ,address lines(A1..A19) and data lines(D0.. D15) in order to access: A byte at odd address [01FF3H] A byte at even address [01FFCH] A word at even address [01FFEH] A word at odd address [01ABFH]Suppose we have a byte-addressable computer using 2-way set associative mapping with 16-bit main memory addresses and 32 blocks of cache. If each block contains 8 bytes, determine the size of the offset field, and show your work.Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes.Q.) What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag and offset fields?
- Can a specific physical address have more than two logical addresses? Give your opinion with examples. Suppose you have a microprocessor which has 16MB of total physical memory. In this case what would be the size of the address bus?Suppose a byte-addressable computer using 4-way setassociative cache has 216 words of main memory (where each word is 32 bits) and a cache of 32 blocks, where each block is four words. Show the main memory address format for this machine. (Hint: Because this architecture is byte addressable, and the number of addresses is critical in determining the address format, you must convert everything to bytes.)In what respects is segmented memory address translation superior than straight translation?
- Consider a computer which uses virtual addressing with 32 bit addresses and a two level page table. The virtual addresses are split into a 9 bit top level page table field, an 11 bit second level page table field and an offset. How large are the pages and, how many are there in the address space?Suppose a specific MCU has the following size of memories: 2 M byte of flash, starting from 0x0800_0000, 256 k byte of SRAM starting from 0x2000_0000, and 8 k byte registers for GPIOs, start at 0x4001_0000. (Note that 0x is the prefix for hexadecimal numbers.) Draw the memory map based on your calculations for the addresses.