The following table shows the memory hierarchy for a 2 GHz processor with the following information: Memory Unit Name Access Speed L1 Cache 1 cycle L2 Cache 20 cycles Main Memory 200 cycles Part 1: What is AMAT on this machine (write your answer in terms of ns)? AMAT = ns Effective CPI = Cache Miss Rate 5% 2% None Part 2: Suppose a benchmark program consists of 20% of load and store instructions, what is the Effective CPI when you consider memory stall cycles? Suppose Base CPI = 1.

The following table shows the memory hierarchy for a 2 GHz processor with the following information: Memory Unit Name Access Speed L1 Cache 1 cycle L2 Cache 20 cycles Main Memory 200 cycles Part 1: What is AMAT on this machine (write your answer in terms of ns)? AMAT = ns Effective CPI = Cache Miss Rate 5% 2% None Part 2: Suppose a benchmark program consists of 20% of load and store instructions, what is the Effective CPI when you consider memory stall cycles? Suppose Base CPI = 1.

Name: 1.3 The following table shows the memory hierarchy for a 2 GHz process
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Description: 1.3 The following table shows the memory hierarchy for a 2 GHz processor with the followinginformation:Memory Unit NameAccess SpeedL1 Cache1 cycleL2 Cache20 cyclesMain Memory200 cyclesPart 1: What is AMAT on this machine (write your answer in terms o

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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