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Translate the following user-level instruction to a microprogram so it can be directly executed by the vertical architecture (VA) attached. 1.b Also show the opcode and register representation in hexadecimal for each finding VA instruction.          B := D – BAND(C+D) if B < 0 GOTO 70;

Translate the following user-level instruction to a microprogram so it can be directly executed by the vertical architecture (VA) attached. 1.b Also show the opcode and register representation in hexadecimal for each finding VA instruction.          B := D – BAND(C+D) if B < 0 GOTO 70;

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Translate the following user-level instruction to a microprogram so it can be directly executed by the vertical architecture (VA) attached. 1.b Also show the opcode and register representation in hexadecimal for each finding VA instruction.

         B := D – BAND(C+D) if B < 0 GOTO 70; 

VERTICAL MICROARCHITECTURE 16 R1 decoder AND 16, R2 decoder Clock Subcycles 16 registers Mmux A latch B latch Increment MPC MAR 256x 12 Control store MBR Micro seq. logic Amux MIR NZ ALU OP R1 R2 OP Decode Shifter RD WR Fig. 4-18. A microarchitecture with vertical microinstructions. Example of OP Assignment for Vertical Architecture OP Instruction 8 IFZ GOTO X; 9 X;= X+ Y; 10 X:= BAND(X, Y); R1 <- X, R2 <- Y 11 X:= Y; 12 X:= NOT (Y); 13 X:= RSHIFT (Y); 14 X:= LSHIFT (Y); 15 MAR := X; MBR := Y; WR; Register Assignment OP Instruction MAR := X; Register Assignment R1 <-X R1, R2 <-X R1 <- X, R2 <- Y 1 X:= MBR; 2 RD; R1 <-X NA R1 <- X, R2 <- Y R1 <- X, R2 <- Y R1 <- X, R2 <- Y R1 <- X, R2 <- Y R1 <- X, R2 <- Y 3 WR; NA 4 MBR := X; R2 < -X 5 ALU :X; R2 <-X NZ; 6 GOTO X; IFN GOTO X; R1, R2 <- X 7 R1, R2 <- X O Focus W
Transcribed Image Text:VERTICAL MICROARCHITECTURE 16 R1 decoder AND 16, R2 decoder Clock Subcycles 16 registers Mmux A latch B latch Increment MPC MAR 256x 12 Control store MBR Micro seq. logic Amux MIR NZ ALU OP R1 R2 OP Decode Shifter RD WR Fig. 4-18. A microarchitecture with vertical microinstructions. Example of OP Assignment for Vertical Architecture OP Instruction 8 IFZ GOTO X; 9 X;= X+ Y; 10 X:= BAND(X, Y); R1 <- X, R2 <- Y 11 X:= Y; 12 X:= NOT (Y); 13 X:= RSHIFT (Y); 14 X:= LSHIFT (Y); 15 MAR := X; MBR := Y; WR; Register Assignment OP Instruction MAR := X; Register Assignment R1 <-X R1, R2 <-X R1 <- X, R2 <- Y 1 X:= MBR; 2 RD; R1 <-X NA R1 <- X, R2 <- Y R1 <- X, R2 <- Y R1 <- X, R2 <- Y R1 <- X, R2 <- Y R1 <- X, R2 <- Y 3 WR; NA 4 MBR := X; R2 < -X 5 ALU :X; R2 <-X NZ; 6 GOTO X; IFN GOTO X; R1, R2 <- X 7 R1, R2 <- X O Focus W
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