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Using the code examples given in Fig. 4 as illustration, explain the differences between the VHDL statements 'if-then-else' and 'case'. Comment briefly on the resultant circuits produced after synthesis. if sel = '00' then dout <= din (0); elsif sel dout <= din (1); elsif sel dout <= din (2); case sel is when '00' => '01' then dout <= din (0); when '01' => '10' then dout <= din (1); when '10' => dout, <= din (2); when others => else dout <= din (3); end if; dout <= din (3); end case; Code A Code B Figure 4

Using the code examples given in Fig. 4 as illustration, explain the differences between the VHDL statements 'if-then-else' and 'case'. Comment briefly on the resultant circuits produced after synthesis. if sel = '00' then dout <= din (0); elsif sel dout <= din (1); elsif sel dout <= din (2); case sel is when '00' => '01' then dout <= din (0); when '01' => '10' then dout <= din (1); when '10' => dout, <= din (2); when others => else dout <= din (3); end if; dout <= din (3); end case; Code A Code B Figure 4

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Using the code examples given in Fig. 4 as illustration, explain the differences between the VHDL statements 'if-then-else' and 'case'. Comment briefly on the resultant circuits produced after synthesis. Q7. if sel dout <= din (0); elsif sel = '01' then dout <= din (1); elsif sel dout <= din (2); '00' then case sel is when '00' => dout, <= din (0); when '01' => dout, <= din (1); when '10' => '10' then else dout <= din (2); dout <= din (3); when others => end if; dout <= din (3); end case; Code A Code B Figure 4
Transcribed Image Text:Using the code examples given in Fig. 4 as illustration, explain the differences between the VHDL statements 'if-then-else' and 'case'. Comment briefly on the resultant circuits produced after synthesis. Q7. if sel dout <= din (0); elsif sel = '01' then dout <= din (1); elsif sel dout <= din (2); '00' then case sel is when '00' => dout, <= din (0); when '01' => dout, <= din (1); when '10' => '10' then else dout <= din (2); dout <= din (3); when others => end if; dout <= din (3); end case; Code A Code B Figure 4
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