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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory but not in the cache, 60 ns are needed to load it into the cache, then the reference is started again. If the word is not in main memory, 12 ms (not ns) are required to fetch the word from disk, then the reference is started again. The cache hit ratio is 0.9 and the main memory hit ratio is 0.06. What is the average time in ns required to access a referenced word on this system?The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions will be ?
- If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?Current server memory modules (DIMMs) employ SEC/DED ECC to protect each 64-bit data block with eight parity bits, as described in Section 5.5. Compare this code's cost and performance to that of the code in 5.9.1. In this case, the number of parity bits is a measure of how much it will cost, while the number of correctable errors is a measure of how well it will function. That one is better, or what?
- The hit rate of the memory closest to the ALU is increased from 75% to 80% in a practical cache memory hierarchy. The hit latency (or hit time) for the closest memory is 20ps, while the miss latency is 20ns. What would the expected reduction in the average memory access latency be?A 32-bit computer has a data cache memory with 8 KB and lines of 64 bytes. Calculate the hit ratio of this program. double a[1024], b[1024], c[1024], d[1024]; // A double occupies 8 bytes , // the array are consecutively stored // in memory for (int i = 0; i < 1024; i++) a[i] = b[i] + c[i] +d[i]; The cache uses a direct mapped function and write-back policy. The cache uses a full associative cache with LRU as replacement algorithm. The cache uses a 2-way associative cache and a 4-way associative cache with LRU as replacement algorithm.Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
- instruction is in the first picture cacheSim.h #include<stdlib.h>#include<stdio.h>#define DRAM_SIZE 1048576typedef struct cb_struct {unsigned char data[16]; // One cache block is 16 bytes.u_int32_t tag;u_int32_t timeStamp; /// This is used to determine what to evict. You can update the timestamp using cycles.}cacheBlock;typedef struct access {int readWrite; // 0 for read, 1 for writeu_int32_t address;u_int32_t data; // If this is a read access, value here is 0}cacheAccess;// This is our dummy DRAM. You can initialize this in anyway you want to test.unsigned char * DRAM;cacheBlock L1_cache[2][2]; // Our 2-way, 64 byte cachecacheBlock L2_cache[4][4]; // Our 4-way, 256 byte cache// Trace points to a series of cache accesses.FILE *trace;long cycles;void init_DRAM();// This function print the content of the cache in the following format for an N-way cache with M Sets// Set 0 : CB1 | CB2 | CB 3 | ... | CB N// Set 1 : CB1 | CB2 | CB 3 | ... | CB N// ...// Set M-1 : CB1 | CB2 | CB…Carefully read each sentence in this question. You may agree/disagree with each sentence (consider each sentence separately) if you have a good justification for doing so (not in more than 2 lines for each sentence). “A daisy chaining technique could result in starvation.” “The received data is saved in contiguous memory regions in DMA transfer.” “The most difficult method of device identification is multiple interrupt lines.” “An interrupt request takes longer for the CPU to handle than a DMA request.” “The architecture of InfiniBand operation is layered.”What is non-uniform memory access (NUMA) and how is it different from conventional memory access?