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What is the maximal length of bit pattern associated with a 6-bit linear feedback shift register?

What is the maximal length of bit pattern associated with a 6-bit linear feedback shift register?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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What is the maximal length of bit pattern associated with a 6-bit linear feedback shift register? (a) (b) By writing down the characteristic polynomial for the linear feedback shift register of figure Q3, or by any other means, prove that the bit pattern associated with this register is not of maximal length. 6-bit parallel out shift register clk reset serial_in Figure Q3 Figure Q4 shows the structure of a static RAM module. State the size of this memory (both number of words and word length). (a) Datain A3 Decoder A2 IN OUT SEL dWR IN OUT SEL dWR HIN OUT SEL dWR IN OUT SEL dWR IN OUTH SEL WR IN OUT SEL dWR A1 IN OUTH IN OUTH A0- WR WR IN OUTH SEL WR IN OUTH IN OUTH SEL WR IN OUTH SEL WR SEL WR IN OUTH SEL WR IN OUTH SEL WR IN OUTH IN OUTH WR WR RW CS A3 A2- Multiplexer Select Dataout Figure Q4 (b) Design and sketch a 32 word memory using the modules of figure Q4 with each word 2 bits wide. (Do not attempt to redraw the internal structure of each module, simply use an outline box for each one with the inputs and outputs shown). Describe any additional logic components used.
Transcribed Image Text:What is the maximal length of bit pattern associated with a 6-bit linear feedback shift register? (a) (b) By writing down the characteristic polynomial for the linear feedback shift register of figure Q3, or by any other means, prove that the bit pattern associated with this register is not of maximal length. 6-bit parallel out shift register clk reset serial_in Figure Q3 Figure Q4 shows the structure of a static RAM module. State the size of this memory (both number of words and word length). (a) Datain A3 Decoder A2 IN OUT SEL dWR IN OUT SEL dWR HIN OUT SEL dWR IN OUT SEL dWR IN OUTH SEL WR IN OUT SEL dWR A1 IN OUTH IN OUTH A0- WR WR IN OUTH SEL WR IN OUTH IN OUTH SEL WR IN OUTH SEL WR SEL WR IN OUTH SEL WR IN OUTH SEL WR IN OUTH IN OUTH WR WR RW CS A3 A2- Multiplexer Select Dataout Figure Q4 (b) Design and sketch a 32 word memory using the modules of figure Q4 with each word 2 bits wide. (Do not attempt to redraw the internal structure of each module, simply use an outline box for each one with the inputs and outputs shown). Describe any additional logic components used.
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