Write a SystemVerilog module for the following function, as defined by the truth table. Use assign statements, and express the equation in minimized sum-of-products (SOP) form. The module declaration for part (a) is below. Fill in the body of the module. Name the other modules: ex1b and ex1c. module ex1a(input logic a, b, c,                     output logic y); // Fill in the body of the module.

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Q: What word describes a product that is inclusive of all inputs to a function?

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