You are given the following cache: Set Index Tag Valid Byte 0 Byte 1 Byte 2 Byte 3 00 49 6E 76 65 21 73 74 20 69 1. FF 1 6E 20 57 6F 1 EB 6C 66 42 79 42 74 65 73 00 64 1 53 61 6D 20 3. F3 1 69 73 20 63 3. 15 6F 6F 6C 00 Memory addresses are 12 bits wide, and the cache is two-way set-associative (E four sets (S = 4). 2) with 4-byte block size and %3D Question 1 TIO What are the bit-widths for the address breakdown fields? Don't include units in your responses, just give numbers. Cache tag width:

Q: sic forms of testing

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