You have a 2-way set associative, write-back cache with 64 bytes in each cache line. Write back is handled by hardware and does not involve any delays. Memory latency is 30 cycles, bandwidth is 8 bytes per cycle. You can choose between: A. 256KB cache with access cost of 1 cycle to read a word into a register, and a miss rate of 15% o B. 1MB cache with a miss rate of 5% but aaccess cost of 2 cycles for every transfer between a register and cache. For each configuration of cache, calculate: size of tag for a cache line, and size of cache addresses (both sizes in number of bits).

You have a 2-way set associative, write-back cache with 64 bytes in each cache line. Write back is handled by hardware and does not involve any delays. Memory latency is 30 cycles, bandwidth is 8 bytes per cycle. You can choose between: A. 256KB cache with access cost of 1 cycle to read a word into a register, and a miss rate of 15% o B. 1MB cache with a miss rate of 5% but aaccess cost of 2 cycles for every transfer between a register and cache. For each configuration of cache, calculate: size of tag for a cache line, and size of cache addresses (both sizes in number of bits).

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

A 1 GByte RAM with 64 word/line is mapped to an 8 kLine Cache with Associative Mapping. What will the address look like?
A computer has a 256 KB, K-way set associative write-back data cache with block size of 32 B. The address sent to the cache controller by the processor is of 32 bits. In addition to the address tag, each cache tag directory contains 2 valid bits and 1 modified bit. If 16 bits are used to address tag. What is the minimum value of K?
A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?
In older processors such as the Intel Pentium or Alpha 21264, the second level of cache was external (located on a diff erent chip) from the main processor and the first level cache. While this allowed for large second level caches, the latency to access the cache was much higher, and the bandwidth was typically lower because the second level cache ran at a lower frequency. Assume a 512 KiB off -chip second level cache has a global miss rate of 4%. If each additional 512 KiB of cache lowered global miss rates by 0.7%, and the cache had a total access time of 50 cycles, how big would the cache have to be to match the performance of the second level direct-mapped cache listed above? Of the eight-way set associative cache?
You have a CPU which contains two processor cores, connected via a bus. Each core has its own 8 row, direct-mapped L1 cache and the two caches are coherent via snoopy cache coherent over the bus, with a write-invalidate mechanism. The block size in the cache is 8 bytes (two words). Core A: Load byte address 63 Core A: Load byte address 57 Core B: Store byte address 63 Core A: Store byte address 63 Core B: Load byte address 102 Core A: Load byte address 121 Core A: Load byte address 57 For each access from the list above, please indicate whether the access would be a hit, a compulsory miss, a conflict miss, a capacity miss, or a coherence miss. Before the sequence begins, both caches are empty. First access (Core A address 63): Second access (Core A address 57): Third access (Core B address 63): Fourth access (Core A address 63): Fifth access (Core B address 102): Sixth access (Core A address 121): Seventh access (Core A address 57):
Suppose you are designing a small, 16KB, 2-way set-associative L1 and a large, 32MB, 32- way set- associative L3 cache for the next processor your company will build. Which one of the following design decisions would you make and why? Justify your choice. Access L1 tag store and data store: in parallel OR series (circle one and explain) Access L3 tag store and data store in parallel OR series (circle one and explain)
Assume that your cache has 2% miss rate for instruction memory and 4% miss rate fordata memory. The miss penalty for instruction memory cache is 100 cycles and for datamemory cache is 200 cycles. The base CPI is 1 cycle.Assume that you have a code which contains 200 instructions and 40% of them areload and store instruction, rest of them are R type of arithmetic instruction. What is thetotal clock cycle to execute the code?Hint: The question is asking the TOTAL clock cycle, not average CPI.
Direct Mapping Cache Problem. Given a Windows XP machine (32-bit architecture) that is byte addressable with 4 Gig memory, 16 K Cache, and a block/line size of 32bytes, calculate Tag, Index, and Offset. Show your work
Ifthere is a 64K cache with a block size of 7k, what is the number of bits in the indes field of block address, given the cache is (3) F Associative, (b) Direct Mapped, (¢) 2-way Sct Associative, and ) 4 - way Set Associative. b
Consider a system with 4GB of memory address space. Assuming a write-back policy and block size of 32 bytes, find the space overhead when it uses a (a) 64 KB direct mapped cache(b) fully associative cache (c) eight-way set-associative cache
A two way set associative cache can host 32 KB (Kilobyte) of memory data with 16-word block. The memory system has 32 bits address bus. How many total bits does this cache have. (include 1 validation bit for each cache line, assume each word is one byte long).
A computer has an average main memory access time of 60 ns. We want to reduce this time to 20 ns by adding a cache, Determine how fast the cache must be (hit time) if we can expect a 90% hit rate of the cache, Show all your work-to get full credit. (Hint: Average memory access time equation)