Essay On Conditional Branch Predictor

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Abstract. Conditional branch predictor (CBP) is an essential component in the design of any modern deeply pipelined superscalar microprocessor architecture. In the recent past, many researchers have proposed varieties schemes for the design of the CBPs that claim to offer desired levels of accuracy and speed needed to meet the demand for the architectural design of multicore processors. Amongst various schemes in practice to realize the CBPs, the ones based on neural computing – i.e., artificial neural network (ANN) have been found to outperform other CBPs in terms of accuracy.
Functional link artificial neural network (FLANN) is a single layer ANN with low computational complexity which has been used in versatile fields of application, …show more content…

The major dificulty encountered due to extensive use of parallelism is the existence of branch instructions in the set of instructions presented to the processor for execution: both conditional and unconditional branch instructions in the pipeline. If the instructions under execution in the pipeline does not bring any change in the control flow of the program, then there is no problem at all. However, when the branch instruction puts the program under execution to undergo a change in the flow of control, the situation becomes a topic of concern as the branch instruction breaks the sequential flow of control, leading to a situation what is called pipeline stall and levying heavy penalties on processing in the form of execution delays, breaks in the program flow and overall performance drop. Changes in the control flow affects the processor performance because many processor cycles must be wasted in ushing the pipeline already loaded with instructions from wrong locations and again reading-in the new set of instructions from right address. It is well known that in a highly parallel computer system, branch instructions can break the smooth flow of instruction fetching, decoding and execution. The consequence of this is in delay, because the instruction issuing must often wait until the actual branch outcome is known. To make things worse, the deeper the pipelining, more is the delay, and thus greater is the performance

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