preview

Instruction Set Computing Essay

Satisfactory Essays
Open Document

Reduced Instruction Set Computing
RISC is based on the insight that simplified instructions allowing tight integration with x86 architecture. In the early 1980’s, the RISC-based machines focused on two critical performance techniques, the exploitation of instruction-level parallelism and the use of caches. The RISC-based computers improved system performance by raising performance bar, forcing prior architectures to keep up or disappear. Hence, the Digital Equipment Virtual Address eXtension (VAX) could not keep up the challenge, and was replaced by RISC architecture. Intel rose to the challenge, by translating 80x86 instructions into RISC-like instructions internally. It adopted many of the innovations first initiated in the RISC designs. …show more content…

1981). Overall, pipelining reduces delay between executing instructions by dividing it into steps so CPU components do not have to sit idle while waiting for other steps of the instruction execution.
In the late 1970s, the industry started applying pipelining in supercomputers. By the mid-1980s, pipelining was used by many different companies around the world to run computers. Today, pipelining is implemented by the instruction unit of most microprocessors. Pipelining will become one of the dominant techniques of large scale integration (LSI) circuit and chip design. By allowing extra bandwidth to be available from the cache, pipelining promises as much as an order of magnitude in performance.
Pipelining increases the CPU instruction throughput, which is the number of instructions completed per unit of time. Without a pipeline, a computer processor gets the first instruction from memory, performs the operation it calls for, and then goes to get the next instruction from memory, and so forth. While fetching the instruction, the arithmetic part of the processor is idle. It must wait until it gets the next instruction. The evolution from RISC to pipelining is to improve system performance in throughput. Pipelining allows simultaneous execution of parts, or stages, of instructions to more efficiently process instructions.
Cache Memory
The CPU uses cache memory to store instructions that are repeatedly

Get Access
Related
Get Access