Medium Voltage, High Power Applications

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medium voltage, high-power applications (e.g. industrial drives, and photovoltaic systems) three-level inverters are used extensively [1, 2]. Recently, the application of these threelevel inverters in low-voltage, high-power traction applications have also been introduced [3, 4]. Amongst different variants of three-level inverter topologies [5], the T-type Neutral-Point- Clamped (T-NPC) inverter, as shown in Fig. 1, has been shown to be the most promising solution for low-voltage, high-power traction applications [4]. Each phase-leg of this topology consists of two devices connected to the neutral-point of the DC-link (inner devices) and two devices placed similar to a conventional two-level inverter (outer devices). In automotive and…show more content…
Previously reported three-level DPWM schemes concluded that at a lower power factor, the three-level DPWM schemes cannot perfectly align the 60° no-switching durations [4, 17] with phase-current peaks, incurring switching instances around current maxima. Thus, their impact on the switching loss reduction is limited during low power factor operation. - Unequal current stress distribution: With conventional three-level modulation strategies, the inner and outer devices are not utilized in a uniform manner [3, 14]. At lower modulation indices, the inner devices carry a substantially higher amount of current compared to the outer devices. This effectively limits the output current capability of the drive when needed most, typically during starting from standstill and during acceleration/deceleration [21]. Additionally, for a T-NPC inverter, the DC-link neutral Jianhong Xu and Jean-Marc Cyr are with TM4 Electrodynamic Systems, Boucherville, QC J4B 8P1, Canada (e-mail: jianhong.xu@tm4.com; jeanmarc. cyr@tm4.com). Discontinuous PWM for Three-Level T-NPC Inverters: Current Re-distribution & Loss Reduction at Low Modulation Index Subhadeep Bhattacharya, Student Member, IEEE, Diego Mascarella, Member, IEEE, Geza Joos, Fellow, IEEE, Jianhong Xu, Member, IEEE, and Jean-Marc Cyr I P O N T1 D1 T2 D2 Tn1 Tn2 Dn1 Dn2 A B C Outer devices Inner devices Fig. 1. Three-level
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