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Nt1310 Unit 6 Ic

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3.1 Problem formulation The goal in this work is to generate robust test architecture optimization for 3D stacked ICs considering the maximum available TAM width in case of uncertainty in TAM configuration. So the problem can be formulated as follows: Given a three dimensional SOC with i) n number of cores, ii) total TAM width limit (TAMmax), and iii) testing time of each core for different TAM widths determine the scheduling order of cores in different configuration with the TAMmax such that the overall testing time is optimized. 3.2 Proposed Algorithm: I have proposed a method, regarding the above mentioned problem. Algorithm is a configuration based robust approach. 3.2.1 Algorithm Description The proposed algorithm takes n cores of different SOCs and grouped them together in different configuration of TAM width like n, 2n, 4n bit. The proposed …show more content…

Now all the cores of the given SOC are assigned randomly to the two divided part of the TAM width. The cores which fall in the same partition of TAM width share same TAM wire hence those cores are in series. Thus we take the summation of test time of all those cores. Similarly the test time of all other cores grouped in other partition are added as those cores are also sharing the same TAM wire, hence in series. But these two partitions of TAM width are in parallel with each other. Thus we take the maximum test time from the two as final test time for the particular partition. Similarly the maximum test time for all possible partition of TAM width is recorded. Now minimum test time among all the maximum test time is recorded which is taken as the final test time for given TAM width in particular configuration. Similarly other minimum test time or other configuration is taken by going for different configuration gives the test time for given TAM width in any of the

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