Electrical Engineering1.) Consider the following series of address references, given as byte addresses:4. 16, 32, 20, 80, 68, 76, 224, 36, 44, 16, 172, 20, 24, 36, 68Label each reference as a hit or miss, and show the final cache contents, for each of the followingcaches. Assume LRU replacement (where appropriate).a.) Direct-mapped, 16x 4-byte blocks.b.) Direct-mapped, 16-byte blocks, total size of 64 bytes.c.) Two-way set associative, 4-byte blocks, total size of 64 bytes.d.) Fully associative, 4-byte blocks, total size of 64 bytes.

Direct mapped don't use LRU ,while fully and set associative use LRU for page replacement.

1.) Consider the following series of address references, given as byte addresses: 4. 16, 32, 20, 80, 68, 76, 224, 36, 44, 16. 172, 20, 24, 36, 68 Label each reference as a hit or miss, and show the final cache contents, for each of the followin caches. Assume LRU replacement (where appropriate). a.) Direct-mapped, 16x 4-byte blocks. b.) Direct-mapped, 16-byte blocks, total size of 64 bytes. c.) Two-way set associative, 4-byte blocks, total size of 64 bytes. d.) Fully associative, 4-byte blocks, total size of 64 bytes.

1.) Consider the following series of address references, given as byte addresses: 4. 16, 32, 20, 80, 68, 76, 224, 36, 44, 16. 172, 20, 24, 36, 68 Label each reference as a hit or miss, and show the final cache contents, for each of the followin caches. Assume LRU replacement (where appropriate). a.) Direct-mapped, 16x 4-byte blocks. b.) Direct-mapped, 16-byte blocks, total size of 64 bytes. c.) Two-way set associative, 4-byte blocks, total size of 64 bytes. d.) Fully associative, 4-byte blocks, total size of 64 bytes.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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3) Assume that there is a cache with 4 blocks and the block size is 1 byte (in total only 4B cache). The cache is initially empty. For two different configurations of the cache; direct-mapped and 2-way set associative, given memory addresses are accessed in the given order. Write if given addresses are hit or miss in the cache. address: 3 - 11 - 0 - 3 - 11
3.0 Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit hexadecimal memory addresses, given as byte addresses. 74, A0, 78, 38C, AC, 84, 88, 8C, 7C, 34, 38, 13C, 388, 18C 3.0.1 For each of these references, identify the index and the tag, given a direct-mapped cache with 8 one-word blocks. List if each reference is a hit or a miss, assuming the cache is initially empty and show every entry to the cache, including the tag value and the addresses of all data items stored. Use hexadecimal or binary, whichever is easier. 3.0.2 For each of these references, identify the index and the tag, given a direct-mapped cache with two word blocks and a total of 16 words. List if each reference is a hit or a miss, assuming the cache is initially empty and show every entry to the cache, including the tag value and the addresses of all data items stored. Use hexadecimal or binary, whichever is easier.
Consider the following list of memory address references. These memory accesses are cached in a cache that has 8 blocks where each block size is two words (2 x 4 bytes). The cache uses direct mapped placement. 0x03, 0xb4, 0x2b, 0x02, 0xbf, 0x58, 0xbe, 0x0e, 0xb5, 0x2c, 0xba, 0xfd a. For each of these references, identify the tag and index field values. b. For each of the references above, identify if each reference is a hit or a miss, assuming the cache is initially empty.
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
1. For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache. Tag Index Offset 31-14 13-7 6-0 a. What is the cache block size (in words)? b. How many entries does this cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
Question 1 Consider a memory system that uses a 32-bit address at the byte level, plus a cache that uses a 64-byte line size. a)Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag b) Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. c) Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in set, number of sets in cache, number of lines in cache, size of tag.
Question 1 Consider the size of main memory as 32 Bytes and the size of cache memory as 8 Bytes. Implement the Set-Associative mapping technique. Do the following: a) Find the number of bits to address 32 bytes in main memory b) Write the formula to map block of main memory to set of cache memory c) Find the block size, line size, set size, tag size d) Draw the figure to show the distribution of main memory in desired blocks containing bytes e) Draw the figure to show the distribution of cache memory in desired lines containing tag numbers, respective blocks, and byte numbers f) Show the tag allocation for each set (and line) of cache memory
a) Assume that a direct mapped cache memory stores 1024 blocks and 64 bytes per block.i) What is storage capacity of the cache memory in bytes?ii) What is length of tag bits if 20 bits addressing is used in CPU?b) Draw a table indicating the initial state (Valid, Tag bits and Data) of a direct mapped cache with 8-blocks and 1 word per block. (Assume that words have 5-bits address length). Then, fill / modify the table (valid, tag and data columns) by accessing word-addresses below in given order. (e.g. old value → new value → ...)5, 10, 26, 5, 10, 23, 20, 5, 23, 10(Show memory accesses by writing Mem[Word Address] in “Data” column)c) Which accesses are “hit” and which accesses are “miss” in question (b)?5, 10, 26, 5, 10, 23, 20, 5, 23, 10
1. Suppose we have a 32KB direct-mapped data cache with 32-byteblocks.a) Show how a 32-bit memory address is divided into tag, index andoffset. Show clearly how many bits are in each field.b) How many total bits are there in this cache?
6 Recall that we have two write policies and two write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 6.1 Buffers are employed between different levels of memory hierarchy to reduce access latency. For this given configuration, list the possible buffers needed between L1 and L2 caches, as well as L2 cache and memory. 6.2 Describe the procedure of handling an L1 write-miss, considering the components involved and the possibility of replacing a dirty block. 6.3 For a multilevel exclusive cache con guration (a block can only reside in one of the L1 and L2 caches), describe the procedures of handling an L1 write-miss and an L1 read-miss, considering the components involved and the possibility of replacing a dirty block.
B) Amain memory address is viewed as consisting of multiple fields. List and define these fields for Direct Mapped Cache, Associative Mapped Cache and Set-associative Mapped Cache Memory.