1. For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache. Tag Index Offset 31-14 13-7 6-0 a. What is the cache block size (in words)? b. How many entries does this cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
1. For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache. Tag Index Offset 31-14 13-7 6-0 a. What is the cache block size (in words)? b. How many entries does this cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
Chapter6: System Integration And Performance
Section: Chapter Questions
Problem 6VE
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1. For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache.
Tag Index Offset
31-14 13-7 6-0
a. What is the cache block size (in words)?
b. How many entries does this cache have?
c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
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