1. Evaluate the CCR and BCC efficiency scores for the following data. Does a CCR efficient DMU always also be a BCC efficient DMU? Is the converse true? DMU 1 2 3 4 5 6 7 8 9 10 Input_1 10 21 9 8 18 12 18 9 10 14 Input_2 12 18 10 8 16 9 15 DEA Problem 9 10 13 Output_1 15 8 11 12 14 17 10 4 10 12 Output_2 9 11 4 12 10 12 10 7 11 15 Output 3 10 9 7 13 7 12 12 5 11 13
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- Suppose we have the following input and output data:DMUInputOutput 1Output 2A221B342C236D512Formulate the efficiency evaluation model for DMU D in (1) a fractional form and (2) a linear programming model form, respectively.A SONET STS-1 SPE is mapped into an STS-1 line. An STS-1 SPE frame consists of 87 columns of 9 bytes, or altogether 783 bytes. There are always 8,000 frames per second. The SPE clock is slower than the line clock by a factor of 5 x 10-7 .On average, we expect to find one pointer adjustment for how many SONET frames?Consider the following MIPS segment code when answering the questions below: sw $t5, 0($t2) sub $t3, $t1, $t6 lw $t1, 12($t5) or $t5, $t1, $t3 Consider running this code on the 5-stage pipelined processor that does not support forwarding and hazard detection. What is the total number of cycles required to execute this code? Consider running this code on the 5-stage pipelined processor that supports forwarding and hazard detection. What is the total number of cycles required to execute this code? How many stalls? How many forwards? What is ALU doing during cycle 7? Can we rearrange the code to minimize the number of cycles and speed up the execution?
- Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?Which kind of parallelism is optimum for SIMD (data or control)? Which kind of parallelism at the level of the program is optimal for MIMD?Draw a Gantt chart to illustrate the execution of P1, P2, P3, P4 and P5 using MultilevelFeedback Queue in single core computing system (Quantum = 8) with the following arrivaltime and burst requirements in the table below.
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