Consider a memory system with a cache access time of 100ns and a memory access time of 1200ns. If the effective access time is 10% greater than the cache access time, what is the hit ratio H?
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Consider a memory system with a cache access time of 100ns and a memory access time
of 1200ns. If the effective access time is 10% greater than the cache access time, what is the
hit ratio H?
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- Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM). The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́ 10-9 secs). (a) What is the overall memory access time given a cache hit rate of 95%? (b) What will the cache hit rate need to be if the overall memory access time in (a) is to be halved?Consider a system with 2 level cache. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns, 10 ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache?Suppose the cache access time is 1 ns, main memory access time is 100 ns and the cache hit rate is 98%. Assuming memory access is initiated with cash access, what is the effective memory access time (round up to 2 digits after the decimal point)
- Consider a two-level memory system (i.e., cache and main memory). Assume the cache access time is 3 clock cycles, and the hit rate is 95%. What should be the main memory access time (penalty) to ensure the memory access efficiency stays at 0.90?Consider a 512 KB cache system used in our laptop. The access time for the cache is 25 ns, and the memory access time is 200 ns. Assuming a miss rate of 25%, what would be the average memory access time?Q. Consider a system with 4-way set associative cache of 256 KB. The cache line size is 8 words (32 bits per word). The smallest addressable unit is a byte, and memory addresses are 64 bits long. (a) How many bits are used for TAG and INDEX fields of cache mapping?
- You are asked to perform capacity planning for a two-level memory system. The first level, M1 is a cache with three capacity choices of 64Kbytes, 128Kbytes, and 256Kbytes. The second level, M2, is a main memory with a 4Mbyte capacity. Let c1 and c2 be the costs per byte and t1 and t2 be the access times for M1 and M2, respectively. Assume c1 = 20 * c2 and t2 = 10 * t1. The cache hit ratios for the 3 capacities are assumed to be 0.7, 0.9 and 0.95, respectively. What is the average memory access time, AMAT, if t1 = 20ns in the three cache designs? (Note that t1 is the time from M1 to CPU and t2 is that from M2 to CPU. This means that t2 includes t1).Consider the following situation: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Based on the fact that each block has 8 bytes, figure out how big the offset field should be, and then show your work.If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?
- Suppose you have a processor with a base CPI 1.0, assuming all references hit in theprimary cache (L1), and a clock rate of 3 GHz. Assume that you have two caches (L1and L2). L2 cache access time is 10 ns and main memory access time is 200 ns,including all the miss handling. Suppose the miss rate per instruction at the L1 cache is10%, L2 cache is 5%.a) What is the effective CPI?b) What will be the effective CPI if we add a new cache (L3) that has 50 nsaccess time and reduce the miss rate to main memory to 1%?Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 with the addition of an L2 cache?Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?