1. Write a Verilog program for a 3-to8 decoder based on the Truth Table 1. You are not allowed to use 2-to-4 decoder to build your 3-to-8 decoder. En A2 A1 0 X 1 1 1 X 。 0 0 1 0 1 AO 0 x 이이이이 0 1 1 1 10 1101 20 21 z2 이이이이이이이이이 0 407 1 1 0 0 |이 oooooo 이석 1 1 010 0 0 M 1 1 24 0 0 데이이이이이이이 1 0 1 1 。 olo 1 Truth Table 1 z5 26 27 이이이이이미 0 비비이이이이이이 이이이이이이 0 0 0 0 1 10 100 111000 000011 |1|1|1|1|0|0 0000 1 (a) Block diagram of the design, the Verilog program, the test bench program and the simulation outputs (text and waveform). (b) Discussion of your design and the results that you obtained

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1. Write a Verilog program for a 3-to8 decoder based on the Truth Table 1. You are not
allowed to use 2-to-4 decoder to build your 3-to-8 decoder.
En A2 A1 AO z0 z1 22 23 24 25 26 27
0x x x 0| 0|0|0| 0 00| 0
000 1 | 1
00000
0000
000
0 10 1
1
0 1|00| 0| 1
1011 0001 1000
1 1|0|0 0 0|0|0|1 1| 0| 0
1 1|0| 1 0|0|0 0 | 0
1 110 0 0000 | 0 1 1
1 1| 1| 1 0|0
1
1
1 0
00
00 1
Truth Table 1
(a) Block diagram of the design, the Verilog program, the test bench program and the simulation outputs
(text and waveform).
(b) Discussion of your design and the results that you obtained
Transcribed Image Text:1. Write a Verilog program for a 3-to8 decoder based on the Truth Table 1. You are not allowed to use 2-to-4 decoder to build your 3-to-8 decoder. En A2 A1 AO z0 z1 22 23 24 25 26 27 0x x x 0| 0|0|0| 0 00| 0 000 1 | 1 00000 0000 000 0 10 1 1 0 1|00| 0| 1 1011 0001 1000 1 1|0|0 0 0|0|0|1 1| 0| 0 1 1|0| 1 0|0|0 0 | 0 1 110 0 0000 | 0 1 1 1 1| 1| 1 0|0 1 1 1 0 00 00 1 Truth Table 1 (a) Block diagram of the design, the Verilog program, the test bench program and the simulation outputs (text and waveform). (b) Discussion of your design and the results that you obtained
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