1.14 Assume a program requires the execution of 50 x 106 FP instructions, 110 x 106 INT instructions, 80 x 106 L/S instructions, and 16 x 106 branch instructions. The CPI for each type of instruction is 1, 1, 4, and 2, respectively. Assume that the processor has a 2 GHz clock rate. 1.14.1 (10] <$1.10> By how much must we improve the CPI of FP instructions if we want the program to run two times faster? wa impro of I (S inctruc
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- Q1: Suppose the hypothetical processor has two I/O instructions: (3+3+3)0011=Load AC from I/O0111=Store AC to I/OIn this case, the 12-bit address identifies a particular external device. Show the program execution using figure for the following program:a) Load AC from device 6b) Add contents of memory location 880c) Store AC to device 7 (Note: Question is to be solved similar to the pictures attached with minimum explaination of a line or two with the steps and SHOULD include the memory location 880 as stated in the question)Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?Assume that a program requires the execution of 125x106 FP (floating point) instructions, 130x106 INT (integer) instructions, 150x106 L/S (load/store) instructions, and 110x106 branching instructions. These instructions have CPIs of 1, 1, 8 and 4, respectively. Assume that the processor has a 5 GHz clock rate. a. Is it possible to run the program twice as fast if we improve the CPI of just the L/S instructions? If so, by how much? Show your calculations. b. What is the Speedup in the execution time of the entire program if the CPI of INT and FP instructions is reduced by 40% and that of L/S and branching instructions is reduced by 50%?
- 10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 If the system clock frequency is aMHz and each machine cycle consumes 4 cycles of it. Calculate the delay time of the LOOP1 loop. Include the execution difference time of the DECFSZ instruction in the last cycle. Select an answerA) 0.6.sB) 6msC)6usD) 60usI ONLY NEED 3 AND 4 Suppose memory has 256KB, OS use low address 20KB, there is one program sequence: Prog1 request 80KB, prog2 request 16KB, Prog3 request 140KB Prog1 finish, Prog3 finish; Prog4 request 80KB, Prog5 request 120kb Use first match and best match to deal with this sequence (from high address when allocated) (1)Draw allocation state when prog1,2,3 are loaded into memory? (2)Draw allocation state when prog1, 3 finish? (3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish (4) Which algorithm is suitable for this sequence ? Describe the allocation process?4.19.16: [5] <COD §4.6>. In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: Also, assume that instructions executed by the processor are broken down as follows: (a) What is the clock cycle time in a pipelined and non-pipelined processor? (b) What is the total latency of an lw instruction in a pipelined and non-pipelined processor? (c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (d) Assuming there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? No hand written and fast answer with explanation
- Consider the code sequence below lw $t1, 4($t0) add $s2, $t1, $t2 lw $t3, 16($t0) add $s3, $t3, $t2 lw $t4, 28($t0) add $s4, $t4, $t2 Suppose there is no forwarding allowed, and for the result of a lw to be consumed by the following R-type of instruction requires 2 bubbles to be placed between the two instructions. Is it possible for the scheduler to juxtapose the commands in such a way that there is no need for any bubbles? If yes, give an example of how it can be done.Answer only 3 and 4 Suppose memory has 256KB, OS use low address 20KB, there is one program sequence: (20) • Prog1 request 80KB, prog2 request 16KB, • Prog3 request 140KB • Prog1 finish, Prog3 finish; • Prog4 request 80KB, Prog5 request 120kb • Use first match and best match to deal with this sequence • (from high address when allocated) • (1)Draw allocation state when prog1,2,3 are loaded into memory? • (2)Draw allocation state when prog1, 3 finish? • (3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish(draw the allocation descriptor information,) • (4) Which algorithm is suitable for this sequence ? Describe the allocation process?4.22 [5] <§4.5> Consider the fragment of LEGv8 assembly below: STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, X4 SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 4.22.1 [5] <§4.5> Draw a pipeline diagram to show were the code above will stall. 4.22.2 [5] <§4.5> In general, is it possible to reduce the number of stalls/NOPs resulting from this structural hazard by reordering code? 4.22.3 [5] <§4.5> Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4.22.4 [5] <§4.5> Approximately how many stalls would you expect this…
- Consider a program that declares global integer variables x, y[10]. Thesevariables are allocated starting at a base address of decimal 1000. All thesevariables have been initialized to zero. The base address 1000 has been placed in$gp. The program executes the following assembly instructions:lw $s1, 0($gp)addi $s1, $s1, 25sw $s1, 0($gp)lw $s2, 12($gp)add $s2, $s2, $s1sw $s2, 8($gp)sw $s2, 12($gp) What are the memory addresses of variables x, y[0], and y[1]? What are the values of variables x, y[0], y[1], and y[2] at the endof the program?We will explore the impact of cache capacity on performance, focusing exclusively on the data cache and excluding instruction storage in the caches. Cache access time is directly linked to its capacity. For the sake of simplicity, let's assume that accessing the main memory takes 100ns, and in a specific program, 50% of instructions involve data access. Two distinct processors, denoted as P1 and P2, are engaged in executing this program. Each processor is equipped with its own L1 cache. L1 size L1 Miss Rate L1 Hit Time P1 64 KB 3.6% 1.26 ns P2 128 KB 3.1% 2.17ns (a) What is the AMAT for P1 and P2 assuming no other levels of cache?Assume a program requires the execution of 75 ×106 FP instructions, 112 ×106INT instructions, 88 ×106 L/S instructions, and 12 × 106 branch instructions.The CPI for each type of instruction is 1, 3, 4, and 2, respectively. Assume thatthe processor has a 2 GHz clock rate.a) By how much must we improve the CPI of FP instructions if we wantthe program to run two times faster?b) By how much must we improve the CPI of L/S instructions if we wantthe program to run two times faster?c) By how much is the execution time of the program improved if theCPI of INT and FP instructions is reduced by 40% and the CPI of L/Sand Branch is reduced by 30%?