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Part(c) : Assume a hypothetical system with eight 32-bit words cache and small Main memory of 1 KB (256 words), the block size is 4-byte, if you know that we use 3 bits to address cache words and 8 bits to address Main memory words. If the system uses Fully Associative mapping given the cache content by the following picture. Complete that following table by typing HIT or Miss for each request made by the CPU : CPU Request 0001011011 Hit/Miss Index Tng Data 000 11001 01 OD010 0010001101 OD100 011 00000 100 10001 101 ODI01 110 11001 111 11100 Cache Mein Memer

Part(c) : Assume a hypothetical system with eight 32-bit words cache and small Main memory of 1 KB (256 words), the block size is 4-byte, if you know that we use 3 bits to address cache words and 8 bits to address Main memory words. If the system uses Fully Associative mapping given the cache content by the following picture. Complete that following table by typing HIT or Miss for each request made by the CPU : CPU Request 0001011011 Hit/Miss Index Tng Data 000 11001 01 OD010 0010001101 OD100 011 00000 100 10001 101 ODI01 110 11001 111 11100 Cache Mein Memer

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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please answer the following question (part c) and explain your answer 

Question 3: Part(a) : Assume that a processor has three levels of memory Level 1 contains 100 word and has an access time of 0.01 usec (u = 10°) Level 2 contains 1000 word and has an access time of 0.5 usec (u = 10°) Level 3 contains 10000 word and has an access time of 0.1 usec (u = 10) Assume that 75% of the access time are found in level 1 memory, 20% in level 2 memory, and 5% in level 3 memory. What is the average time to access a word ? Answer : Part (b) : Assume that the cache has 64 lines. Each line consists of 4 words. Now consider that the RAM of this system has 1024 bytes. Assuming direct mapping of RAM to Cache. Answer the following questions : 1) identify the number of bits required to access 1024 bytes of RAM Le, number of bits required for The RAM ? 2) Identify the number of bits required for accessing a Word in the line? 3) Identify the number of bits required to access the 64 lines of cache ? 4) Identify the size of Tag required for identifying the block of RAM that is present in the Cache line? 5) identify the line number in the cache to which the following RAM address maps? Also, identify the TAG for this address? RAM address = 10 1001 1101 Part(c) : Assume a hypothetical system with eight 32-bit words cache and small Main memory of 1 KB (256 words), the block size is 4-byte, if you know that we use 3 bits to address cache words and 8 bits to address Main memory words. If the system uses Fully Associative mapping given the cache content by the following picture. Complete that following table by typing HIT or Miss for each request made by the CPU : CPU Request Hit/Miss Index Tag Data 000 11001 0001011011 0010001101 01 OD010 010 OD100 011 00000 100 10001 101 O0101 110 11001 111 11100 Cache Main Memery
Transcribed Image Text:Question 3: Part(a) : Assume that a processor has three levels of memory Level 1 contains 100 word and has an access time of 0.01 usec (u = 10°) Level 2 contains 1000 word and has an access time of 0.5 usec (u = 10°) Level 3 contains 10000 word and has an access time of 0.1 usec (u = 10) Assume that 75% of the access time are found in level 1 memory, 20% in level 2 memory, and 5% in level 3 memory. What is the average time to access a word ? Answer : Part (b) : Assume that the cache has 64 lines. Each line consists of 4 words. Now consider that the RAM of this system has 1024 bytes. Assuming direct mapping of RAM to Cache. Answer the following questions : 1) identify the number of bits required to access 1024 bytes of RAM Le, number of bits required for The RAM ? 2) Identify the number of bits required for accessing a Word in the line? 3) Identify the number of bits required to access the 64 lines of cache ? 4) Identify the size of Tag required for identifying the block of RAM that is present in the Cache line? 5) identify the line number in the cache to which the following RAM address maps? Also, identify the TAG for this address? RAM address = 10 1001 1101 Part(c) : Assume a hypothetical system with eight 32-bit words cache and small Main memory of 1 KB (256 words), the block size is 4-byte, if you know that we use 3 bits to address cache words and 8 bits to address Main memory words. If the system uses Fully Associative mapping given the cache content by the following picture. Complete that following table by typing HIT or Miss for each request made by the CPU : CPU Request Hit/Miss Index Tag Data 000 11001 0001011011 0010001101 01 OD010 010 OD100 011 00000 100 10001 101 O0101 110 11001 111 11100 Cache Main Memery
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