10. Q1 : What is an atomic instruction? Show that if the wait operation is not executed atomically, then mutual exclusion may be violated Q2: What is spinlock? Discuss the advantage and disadvantage of using spinlock. Why do you think Solaris, Linux, and Windows 2000 use spinlocks as a synchronization mechanism only on multiprocessor systems and not on single- processor systems?

10. Q1 : What is an atomic instruction? Show that if the wait operation is not executed atomically, then mutual exclusion may be violated Q2: What is spinlock? Discuss the advantage and disadvantage of using spinlock. Why do you think Solaris, Linux, and Windows 2000 use spinlocks as a synchronization mechanism only on multiprocessor systems and not on single- processor systems?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
a) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Suppose T1 does “Load X into register R1” machine instruction. Then the CPU scheduler switches the CPU to T2. Will T2 see the same vaue of R1 as loaded here by T1? (YES or NO)? Explain in less than 50 words. Be specific. (b) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Is it possible to have a moment (time instant) where both threads have made a request to Memory Unit to read some data (ex. as part of a “Load … into register …” instruction) and Memory Unit has not yet completed either of these two requests? Explain in less than 50 words.
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Please help me in these following questions: 1/ The LEGv8 processor in the book demonstrated multiple issue using __________ . a. dynamic dual issue b. dynamic quad issue c. static dual issue d. static quad issue 2/ A stall in the pipeline is indicated by the compiler using a(n) __________ instruction. a.branch b. exception c. nop d. delay 3/ The CPU is updated on the __________ . a. low clock value b. falling clock edge c. rising clock edge d. high clock value 4/ If an exception occurs in the pipeline, the following must occur. a. Flush all instructions b. Complete instructions before the exception, flush the instructions following the exception c. Complete instructions before the exception, save the registers of the instructions following the exception d. Complete all instructions except for the failed instruction 5/ Dynamic multiple issue occurs __________ . a. at compile time b. when the CPU fetches instructions c. when a hazard invalidates an instruction d. when a…
How would it be advantageous to prioritize the I/O queue above the process execution queue? What will happen if the I/O is interrupted is anyone's guess. Indications are conflicting as to how this could effect the maximum burst rate of the CPU. I'm confused as to the nature of your question.
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Discuss the role of the instruction window in dynamic multithreading and how it manages instruction scheduling.
please answer with proper explanation and step by step solution. Question As a simple model of a bus-based multiprocessor system without caching, suppose that one instruction in every four references memory, and that a memory reference occupies the bus for an entire instruction time. If the bus is busy, the requesting CPU is put into a FIFO queue. How much faster will a 64-CPU system run than a 1-CPU system? Note: Don't copy paste from online website.
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