10. Which of the following does not interrupt a running process? A. A device B. Timer C. Scheduler process D. Power failure 11. Manager's salary details are hidden from the employee. This is: A. Conceptual level data hiding B. Physical level data hiding C. External level hiding D. None of the above
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- QUESTION 2 Discuss with examples the main difference between system programming and application programming and explain in your own words how each of these can be carried out in the computer system. With your knowledge in memory addressing modes and using the given opcodes LDA = 00 0000 0000 (00) 0 (x) What will be the content of the address loaded into the accumulator? b. With your knowledge in memory addressing mods and using the given opcodes STCH = OX54 Buffer = 1000 0101 0100 (00) 1 (x) 000 1000 0000 0000 () 011 0000 0000 0000 () What will be target address? Briefly explain the usage of the JSUB and RSUB instruction sets in an SIC architecture coding1) For a Pentium II descriptor that contains a base address of 0004B100H, a limit of 00FFFH, and G = 1, what starting and ending locations are addressed by this descriptor? 2) Code a descriptor that describes a memory segment that begins at location 0005CF00h and ends at location 00060EFFh. The memory segment is a data segment that grows upward in the memory system and can be written. The segment has a user level privilege (lowest) and has not been accessed. The descriptor is for an 80386 microprocessor.Please help with the following in regards to Nand2Tetris, and hack code, so hack assembly and hack vm. There can be more that one answer to a question if so please explain why. 1a. The A-instruction in the Hack computer performs a. direct addressing. b. immediate addressing. c. indirect addressing. d. bitwise addressing. 1b. Each memory address in the Hack computer references a. a single byte. b. a single word. c. multiple words. d. the D-register 1c. Given the following assembly code: (FOO) @FOO 0;JMP The purpose of the code is to : a. test of the value is = = 0 NO-OP b. jump to address 0 in RAM c. return a 0 to the calling code d. create an endless loop e. end the assembly language program 1d. Given a function called foo() that calls another external function bar() which in turn calls a second function called additup(). Indicate the VM line of code indicating the location in the program that control should be return to: a.@Foo.$bar. b. @Foo$bar$additup.ret.1 c.…
- 1. Name all of the general purpose registers and some of their special functions. 2. How are the segment registers used to form a 20-bit address? 3. (a) If CS contains 03E0H and IP contains 1F20H, from what address is the next instruction fetched? (b) If SS contains 0400H and SP contains 3FFEH, where is the top of the stack located? (c) If a data segment deigns at address 24000H, what is the address of the last location in the segment? 4. Explain what the instruction array and data caches are used for. 5. What is the EU and BIU, and what purpose in the microcomputer? 6. Two memory locations, beginning at address 3000H, contain the bytes 34H and 12H. What is the word stored at location 3000H? See Figure 2.26 for details. Address 3000 Data 34 3001 12 Figure 2.26 For question 6 7. What is a physical address? What are the differences between the 8086 logical and physical memory maps? 8. May memory segments overlap? If so, what is the minimum number of overlapped bytes…On a uniprocessor, portion A of program P consumes 24 seconds, while portion B consumes 822 seconds. On a parallel computer, moderately serial portion A speeds up 4 times, while perfectly parallel portion B speeds up by the number of processors. 1- What is the speedup of program P on 1,024 processors? _______ times 2- How many processors are required to achieve at least half the theoretical maximum possible speedup on P?The PowerPC uses a hardware managed TLB with an inverted page table. Discuss its advantages and disadvantages. i.e., What are the implications of the inverted page table on the size of each page table entry? What about a page table walk (how many memory references are potentially required on a TLB miss)? Are per-process page tables necessary or can they be eliminated?
- A recent paper proposed eliminating paging and using segmentation instead.Their reasoning was that memories can be made large enough to avoid usingvirtual memory in most cases. Suppose we adopt this philosophy and requirethat all memory references refer to a segment descriptor. Give a design forsuch a descriptor. What changes would you make to the RISC-V instructionset and architecture?This question is on Computer Architecture. Translate the following arithmetic and logical expressions written in C programming language intoinstructions sequences written in MIPS Assembly language. You may assume that the values (orbase addresses) of the variables a, b, c, and d are in the general-purpose registers $s0, $s1,$s2, and $s3. 1. d[3] = a - b + c[7];2. c[5] = (a << 3) & (b >> 2);Here, <<, >>, and & indicate the bitwise left-shift, right-shift, and AND operations respectively.Topic: 8086 microprocessor Q 1c) AL= 53 CL=29 ADD AL, CL DAA What is the value of AL after execution? Q 1d) MOV AL, 4929H, what will be the value of AL after execution?
- I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.onvert the following C code snippet into the corresponding x86 assembly instructions. 1) if(x error_outlineHomework solutions you need when you need them. Subscribe now.arrow_forward Question Asked Aug 11, 2020 1 views Convert the following C code snippet into the corresponding x86 assembly instructions. 1) int n = 5; for(int i = 0; i <= 10; i++) { cout<<n<<” x ”<<i<<” = ”<<n*i<<endl; }