Answered: Discuss with examples the main…

Discuss with examples the main difference between system programming and application programming and explain in your own words how each of these can be carried out in the computer system.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 1RP

See similar textbooks

Related questions

Q: On a typical microprocessor, a distinct I/O address is used to refer to the I/O data reg- isters and…

A: There are two I/O instruction formats utilized in the Intel 8088. In one format, an 8-bit port…

Q: 6. Suppose that the interrupt processing method of is to store the breakpoint in the address of…

A: Input yield gadget gives the intrudes. The Processor completes the execution of a guidance prior to…

Q: 2) A computer uses a memory unit of 1048576K word made of 50 bit each. A binary instruction code is…

A: Note: Answering the first three subparts i.e. a,b, and c. Given Data : Size of memory word(s) =…

Q: would it be possible to make the machine thrash assuming that you have a reasonable virtual memory…

A: Yes it is possible to make the machine thrash assuming that you have a reasonable virtual memory…

Q: 5. On a non-pipelined sequential processor, a program segment, which is a part of the interrupt…

A: The answer is

Q: Given the X86-64 assembly instructions below, suppose variable "a" and "b" are long int data…

A: Lets do this line by line : 1. movq %rbx , %edx This moves the contents of register rbx into edx.…

Q: Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively.…

A: Given that Assume that two numbers: dividend and divisor are saved in memory address M1 and M2…

Q: 4. Suggest and explain X86 addressing modes that can obtain operands from a a. Static memory…

Q: Which one of the following is true with regard to a CPU having a single interrupt request line and…

A: Please comment in case of any doubt

Q: Question 3 Suppose during an execution of an instruction, the Stack Pointer register had the value…

A: a) The Value Of the Flag Register is Pressed. It means that first the value of the Stack Pointer is…

Q: 23)The last action taken by the CPU in the fetch-execution cycle is: a. IR[address] --> MAR b. PC +…

A: Here, we are asked the last action taken by the CPU in the fetch-execution cycle is. During…

Q: The following is SM chart implemented using single address microprogramming. -Assign each state…

A: The algorithmic state machine is a strategy for planning limited state machines It is utilized to…

Q: 4. Memory and Addressing Modes The state of the CPU and memory is represented by this diagram.…

A: EXPLANATION Below is the answer for the given question. Hope you understand it well. If you have any…

Q: Question 2: Given the ending address and memory location address, determine the segment register…

A: Below I have solved the question on time .

Q: Question Write an assembly code to implement the y = (x1+x2) * (x3+x4) expression on 2-address…

A: The assembly code for 2-address machine is given by Load R1,x1 // loads x1 to R1 Load R2,x2…

Q: What is the function of the instruction pointer ? a- The IP and the CS are used to point to…

A: Explanation: The last register of interest is the IP (instruction pointer) register. This 32-bit…

Q: 1. The table below presents a list of devices that are to be addressed in a certain memory space.…

A: Here is the solution for the first problem

Q: A simple processor shown in the figure, having the following basic calculation ability: Addition…

A: On a computer, a memory address (MAR) register is a CPU that stores the address where the data will…

Q: CPU Main Memory Instructions Space MAR ALU MBR AC BUS PC Control Data Space Cache A simple processor…

A: the answer is given below:-

Q: interface four chips of 128k×8 SRAM to 8086 microprocessor using separate bank write strobes such…

Q: An interrupt from a CPU causes the processor to halt what it is doing and react to the signal…

A: The answer is...

Q: Table of pointers for interrupt to be executed contains the a. interrupts b. programs c. addresses…

A: A pointer is a variable which holds the address of another variable

Q: Question 2 nt of an assembly language program. a time and write the new resulting C, Registers…

A: in this question we explain one by one instructions. Here NZVC is a flages (negative,zero, overflow…

Q: 6. (1)Draw a diagram to show that how a logical address is translated into a linear address and to a…

A: 1. Draw diagram to show that how logical address is translated into linear address and into physical…

Q: For a particular computer architecture, the ISA consists of a total of 70 different operations. The…

A: Below is the answer to above question. I hope this will be helpful for you.

Q: A computer employs RAM chips of 128 x 8 and ROM chips of 512 x 8. The computer system needs 256…

A: a) 8 RAM chips and 4 ROM chips are reqyuired. Explanation: RAM chip size =256*8 Required memory…

Q: microprocessors are to be interfaced to a system bus. The following details are given: All…

A: The answer given as below:

Q: 2- Given a control memory microinstruction size of 30 bits. Change the instruction shown in Figure…

A: Given that: Control memory size = 30 bits F1 = 3 bits F2 = 3 bits F3 = 4 bits BR = 2 bits CD = 2…

Q: memory range from 0xA000 to 0xCFFF (inclusive) Your design must be subject to the followi

A: The system has 3 microprocessors and shared memories are there for all the processors. there will be…

Q: (a) In the given 8086 block diagram, write down the sizes of the (i) registers (ii) segments (iii)…

A: The answer is given below:-

Q: 4. Memory and Addressing Modes The state of the CPU and memory is represented by this diagram.…

A: EXPLANATION Below is the answer for the given question. Hope you understand it well. If you have any…

Q: 2. Given the following series of instructions (left two columns). After each instruction has been…

A: In computer engineering, computer architecture is a set of rules and methods that describe the…

Q: The register content for an Intel 8086 microprocessor is as follows:CS = 1000H, DS = 2000H, SS =…

A: The register contents of 8086 microprocessor are given. a)MOV [SI],AL In this instruction the…

Q: Suppose we have the instruction Load 0000. Given memory and register R1 contain the values below: R1…

A: Answer: We need to write the how to load into accumulator using the following addressing mode. So we…

Q: Explain the difference between Preindexed and Postindexed addressing mode with an example. Write an…

A: Pre-indexed The offset is combined with the value in the base register, and the base register is…

Q: Problem Given the following memory values and a one-address machine with an accumulator, what…

A: a) Immediate addressing mode loads the constant value 20 as an operand to accumulate. AC=20

Q: Question 01 : (a) Write an assembly language program for the Intel 8086 microprocessor that adds two…

Q: the number of words (Memory locations) found in each memory device for the given numbers of address…

A: The number of words (Memory locations) found in each memory device for the given numbers of address…

Q: Assume that the operation times of one add instruction for the major functional units are 325 ps for…

A: The operation times of one add instruction for the major functional units are 325 ps for memory…

Q: Near and Far Call in 8086

A: Note: There are multiple questions are given in one question. According to the rule, you will get…

Q: witch of the following is the mode of addressing specifies the index of a register where the value…

A: ADDRESSING MODE:In the computer architecture the addressing mode which specifies the operands of an…

Q: Consider a 1-address CPU that has a memory unit with 128K words of 32 bits each. An instruction is…

A: Size of 1 word = 32 bits Size of instruction = 1 word = 32 bits Addressing mode = 2 bits Register…

Q: For the 8086 microprocessor, show the physical addresses and the contents of memory after execution…

A: The DW,DD and DB are data declaration directives 1. DW: Directive used to declare Word type…

Q: 2-The elements of the ISA for a particular type of CPU include a. addressing modes b. data…

A: QUESTION 1 The elements of the ISA for a particular type of CPU include CORRECT OPTION : (E) a, b…

Q: Question 2: Given the ending address and memory location address, determine the segment register…

Q: Question 1 Suppose that on a given single cycle CPU it takes: • 40 nanoseconds to read a word from…

A: Note : as per company's guidelines we are supposed to answer only one question at a time in case…

Q: Draw the complete block diagram for an 8086 Microprocessor system with two PPIs, where the address…

A: Block Diagram of 8086 Microprocessor with PPIs The architecture of 8086 microprocessor is composed…

Concept explainers

Fundamentals of Input and Output Performance

The I/O subsystem is a component of computer system design that uses buses to assist communication between the Central Processing Unit, Computer Memory/Storage, and Input and Output Devices (that is known as peripheral devices). The I/O subsystem includes disc controllers, tape drives, discs, system buses, and other devices. The I/O database application reads and writes drives using the operating system windows I/O.

Question

QUESTION 2

Discuss with examples the main difference between system programming and application programming

and explain in your own words how each of these can be carried out in the computer system.

With your knowledge in memory addressing modes and using the given opcodes

LDA = 00

0000 0000

(00)

(x)

What will be the content of the address loaded into the accumulator?

b. With your knowledge in memory addressing mods and using the given opcodes

STCH = OX54

Buffer = 1000

0101 0100

(00)

(x)

000 1000 0000 0000

()

011 0000 0000 0000

()

What will be target address?

Briefly explain the usage of the JSUB and RSUB instruction sets in an SIC architecture coding

Process by which instructions are given to a computer, software program, or application using code.

Expert Solution

This question has been solved!

Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.

SEE SOLUTION Check out a sample Q&A here

Step 1

VIEW

Step 2

VIEW

Step by step

Solved in 2 steps

SEE SOLUTION Check out a sample Q&A here

Knowledge Booster

Fundamentals of Input and Output Performance

Learn more about

Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.

Similar questions

Most Intel CPUs use the __________, in which each memory address is represented by two integers.
How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?
So, what are your thoughts on the importance of having many addressing modes in a computer system?
CPUs with either a synchronous or asynchronous memory bus are preferable. Thanks. The way you arrived at this conclusion needs explaining.
We want to build a word organized main memory of 8 GB for a 32-bit CPU architecture composed of word organized memory modules of 30-bit address and 8-bit data buses each. a) Draw the interface of the main memory by clearly indicating the widths of the buses. b) Howmanymemorymoduleswouldbenecessarytobuildthememorysystem? c) Design the main memory internal organization built out of the above memory modules (use multiplexers and/or decoders as needed) by clearly indicating the widths of the used busses d) CanweusethismemorysystemasRAMfortheCPUinProblem1?Explainyouranswer.
We want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed ofbyte organized memory modules of 30-bit address and 8-bit data buses each.a) Draw the interface of the main memory by clearly indicating the widths of the buses.b) How many memory modules would be necessary to build the memory system?c) Design the main memory internal organization built out of the above memory modules (usemultiplexers and/or decoders as needed) by clearly indicating the widths of the used bussesd) Can we use this memory system as RAM for the CPU in Problem 1? Explain your answer.
Suppose that you were to design an advanced computer architecture that did process switching in hardware, instead of having interrupts. What information would the CPU need? Describe how the hardware process switching might work.
4 Memory and Addressing Modes The state of the CPU and memory is represented by this diagram. ey Wemory Address | Value Value |0 [0 |1(0]|0|0(1]1 a) Value of A after execution of LDA #50D? b) Value of A after execution of LDA #50F? ©) Value of ¥ after execution of LOY $0D? d) Value of Y after LDY $(000F), X? ) Value of Y after LDY ($0F), X2 please show workings!
What are your opinions on the need for many addressing modes in a computer?
What are your thoughts on the need for many addressing modes in a computer system?
Which is likely to be longer (have more instructions): a program written for a zero-address architecture, a program written for a oneaddress architecture, or a program written for a two-address architecture? Why?
What is the organization of the general purpose registers in parts for the 32 bit computerarchitecture? Explain in what programming scenarios with regards to the data typesinvolved you would use either of these parts and why. in assembly language