12. Consider a virtual memory system running on a RISCCPU. Page tables are not lockedin memory and may be swapped to disk. An lw (load word) instruction reads onedata word from memory; the address is the sum of the value in a register and animmediate constant stored in the instruction itself. Neither machine instructions norpage-table entries nor data words can cross a page boundary. In the worst case, howmany page faults could be generated as a result of the fetch, decode, and execution ofan lw instruction?

In CPU has address,say A2 of the data word that needs to be loaded.we will look into page table,in…

Answered: 12. Consider a virtual memory system…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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please no chatgpt answer . Consider a demand-paging system with a paging disk that has an average access and transfer time of 20 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference, if the page-table entry is in the associative memory. Assume that 80 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2 percent of the total) cause page faults. What is the effective memory access time? Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6. Assuming demand paging with four frames, Show which pages are resident under the LRU, FIFO, and Optimal replacement algorithms by filling out the following tables. How many page faults would occur…
Consider a demand-paging system with a paging disk that has an average access and transfer time of 25 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference if the page-table entry is in the associative memory. Assume that 75 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2.5 percent of the total) cause page faults. What is the effective memory access time?
A computer uses virtual memory, and a new solid-state drive (SSD) as space for paging. Refer to the last ppt file. In the case presented there, the hard disk drive (HDD) required 25 ms to read in a page, and a rate of 1 page fault per 1000 references introduced a 250 slowdown. If the SSD offers a time of only 80 µs, what is the slowdown in performance caused by 1 pf per 1000 references (you are not concerned with dirty vs. clean pages). What is the maximum rate of page faults you can accept if you want no more than a 5% slowdown in execution using virtual memory? Know your metric prefixes and symbols for time: s for seconds, ms for milliseconds, µs for microseconds, ns for nanoseconds.
In the working set model, the idea is to examine the most recent delta page referances. It is also known as an approximation of the Program's Locality. If the total demand is greater than the total number of available frames (D>m) then it will cause thrashing, because in this case, some processes will not have enough frames. Below you see 3 processes and their excepted memory references during their execution. When will the thrashing happen to occur according to the working set model? Assume total memory(m) is 10 and Delta is 5
Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let τ be the access time for the two L1 caches. Themiss penalties are approximately 15τ for transferring a block from L2 to L1, and 100τ fortransferring a block from the main memory to L2. For the purpose of this problem, assumethat the hit rates are the same for instructions and data and that the hit rates in the L1 andL2 caches are 0.96 and 0.80, respectively.(a) What fraction of accesses miss in both the L1 and L2 caches, thus requiring accessto the main memory?(b) What is the average access time as seen by the processor?(c) Consider the following change to the memory hierarchy. The L2 cache is removedand the size of the L1 caches is increased so that their miss rate is cut in half. Whatis the average memory access time as seen by the processor in this case
Page tables are used to translate logical memory addresses into physical memory addresses. If the single-level page table scheme is applied, how many memory accesses are required for each load/store operation (if Translation Lookaside Buffer is not considered)? ________________ If the three-level page table scheme is applied, how many memory accesses are required for each 4 load/store operation (if Translation Lookaside Buffer is not considered)? ________________ If the hashed inverted page table scheme is applied, how many memory accesses are required for each load/store operation (if Translation Lookaside Buffer is not considered)?
In this exercise, we will examine space/time optimizations for page tables. The following list provides parameters of a virtual memory system. Virtual Address (bits) Physical DRAMInstalled Page Size PTE Size (byte) 43 16 GiB 4 KiB 4 For a single-level page table, how many page table entries (PTEs) are needed? How much physical memory is needed for storing the page table? Using a multilevel page table can reduce the physical memory consumption of page tables, by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB? An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common case and worst case numbers of memory references needed for servicing a TLB miss?
Consider a 32-bit computer with the MIPS assembly set, that executes the following code fragment loaded in memory in the address 0x0000000. li $t0, 1000 li $t1, 0 li $t2, 0 loop: addi $t1, $t1, 1 addi $t2, $t2, 4 beq $t1, $t0, loop This computer has a 4-way associative cache memory of 32 KB and lines of 16 bytes. Calculate the number of cache miss of the previous code, and the hit ratio, assuming that no other program is executing and that the cache memory is initially empty.
Answer only 3 and 4 Suppose memory has 256KB, OS use low address 20KB, there is one program sequence: (20) • Prog1 request 80KB, prog2 request 16KB, • Prog3 request 140KB • Prog1 finish, Prog3 finish; • Prog4 request 80KB, Prog5 request 120kb • Use first match and best match to deal with this sequence • (from high address when allocated) • (1)Draw allocation state when prog1,2,3 are loaded into memory? • (2)Draw allocation state when prog1, 3 finish? • (3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish(draw the allocation descriptor information,) • (4) Which algorithm is suitable for this sequence ? Describe the allocation process?
Find the AMAT for a processor with a 1 ns clock cycle time, a miss penalty of 15 clock cycles, a miss rate of 0.1 misses per instruction, and a cache access time (including hit detection) of 2 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.
Suppose we have a system with 8-byte words and a cache with 32-byte blocks connected directly to memory. The cache has a hit time of 10 ns. The bus to memory is 8 bytes wide, requesting a word from memory takes 100 ns (total, aka round trip time), and memory bus transactions are serialized (not pipelined). The baseline cache requests each word from memory sequentially on a miss, and waits to respond to the CPU until miss repair is fully complete. Consider a workload with poor locality, with a cache hit rate of only 20%. Show your work. (a) What is the AAT speedup of early restart over baseline? Assume a uniform distribution of accesses to each word in a block (25% chance of each). This means that 25% of misses are for word 1 in a block, 25% for word 2, 25% for word 3, and 25% for word 4. (b) What is the AAT speedup over baseline of early restart if the distribution of accesses to each word in a block is 5%, 15%, 30%, and 50%, respectively? (c) What is the AAT speedup over baseline with…
For an old computing system with 2K bytes physical memory, and the virtual address has 13bits. Suppose that the size of page/frame is 256 bytes. For a process A, it has its codes and data inpage 0, 1, 2, 10, 11, 28, 29, where pages 0, 1, 10, 29 are in frame 1, 3, 4 and 6, respectively.Moreover, frame 0 contains kernel OS code/data and all other frames are free.a. Show the page table and the content of each PTE for process A;b. Use a figure to illustrate the address translation for virtual address 1110000100000 and explainwhat happens during the translation (interaction among page table, physical memory, disk, andoperating system);c. Suppose that there is a TLB with 4 entries and the current content has the mapping informationfor pages 0, 1. Draw a new figure to illustrate the translation of address 101000011000 andexplain what happens during the translation process.

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