Consider a paging system with the page table stored in memory. Memory access takes 200 nanoseconds. If we add associative registers (a TLB), and 75 percent of all page table references are found in associative registers, then the effective memory reference time is__ns Assume that finding a page-table entry in the TLB takes zero time.

Consider a paging system with the page table stored in memory. Memory access takes 200 nanoseconds. If we add associative registers (a TLB), and 75 percent of all page table references are found in associative registers, then the effective memory reference time is__ns Assume that finding a page-table entry in the TLB takes zero time.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 12RQ

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Consider a paging system with the page table stored in memory.a. If a memory reference takes 400 nanoseconds, how long does a paged memoryreference take?b. If we add TLBs, and 95 percent of all page-table references are found in the TLBs,what is the effective memory reference time? (Assume that finding a page-table entry inthe TLBs takes zero time, if the entry is there.)
(b) Consider a paging system with the page table stored in memory. If a memory referencetakes 200 nano seconds, how long does a paged memory reference take? If we add a TLB,and 75% of all page references are found in the TLB, what is the effective memory referencetime? (Assume that it takes zero time to find an entry in the TLB if it is already present).
Consider a demand-paged system where the page table for each process resides in main memory. In addition, there is a fast associative memory (also known as TLB which stands for Translation Look-aside Buffer) to speed up the translation process. Each single memory access takes 1 microsecond while each TLB access takes 0.2 microseconds. Assume that 2% of the page requests lead to page faults, while 98% are hits. On the average, page fault time is 20 milliseconds (includes everything: TLB/memory/disc access time and transfer, and any context switch overhead). Out of the 98% page hits, 80 % of the accesses are found in the TLB and the rest, 20%, are TLB misses. Calculate the effective memory access time for the system.
Consider a paging system where the page table is stored in fast access registers (TLB) with an access time of 10 nanoseconds and a hit ratio of 80%. Memory access time is 100 nanoseconds (only one memory access). Assume that when a process generates a page fault, one of the processes pages currently in main memory will have to be replaced and that 60% of the time the page to be replaced has been modified. Assume that it takes 20 milliseconds to service a page fault if the page to be replaced has been modified and 10 milliseconds if it has not been modified. What is the page fault rate for an effective memory access time of 240 nanoseconds? Explain your steps and calculations.
Consider a memory-management system based on paging. The total size of the physical address space 64 MB, Pages of size 4 KB, the Logical address space of 4GB. total number of pages are 16384, total number of frames are 16384 and the number of entries in a page table are 1048576.Now Calculate: a)Size of Page Table b) No of bits in Physical Address c) No of Bits in Logical Address
please no chatgpt answer . Consider a demand-paging system with a paging disk that has an average access and transfer time of 20 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference, if the page-table entry is in the associative memory. Assume that 80 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2 percent of the total) cause page faults. What is the effective memory access time? Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6. Assuming demand paging with four frames, Show which pages are resident under the LRU, FIFO, and Optimal replacement algorithms by filling out the following tables. How many page faults would occur…
Consider a demand-paging system with a paging disk that has an average access and transfer time of 25 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference if the page-table entry is in the associative memory. Assume that 75 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2.5 percent of the total) cause page faults. What is the effective memory access time?
On a simple paging system with 224 bytes of physical memory, 256 pages of logical address space, and a page size of 210 bytes. 1. How many bits are needed to store an entry in the page table (how wide is the page table)? Assume a valid/invalid 1-bit is included in each entry. 2. If the page table is stored in the main memory with 250nsec access time, how long does a paged memory reference take? 3. If the page table is implemented using associative registers that takes 95nsec. and main memory that takes 200nsec, what is the total access time if 75% of all memory references find their entries in the associative registers?
In an Additional-Reference-Bits LRU Approximation Algorithm, each page has an 8-bit shift register. The bit associated with each page referenced is set (to 1) by the hardware. These 8-bit shift registers contain the history of page use for the last eight time periods. The register value of the 8 pages are as given: 1. 00100010 2. 11000100 3. 00010111 4. 11100111 5. 11110111 6. 10000011 7. 01010111 8. 00000011 Which page will be replaced by the LRU Approximation Algorithm last? Which page will be replaced by the LRU Approximation Algorithm first?
Consider a cache memory with blocks of 23 = words (1 word = 4 bytes) , with a bus Main Memory - Cache of 32 bits, and with 1 clock cycle to send the address, a row cycle time (DRAM) of 17 cycles (5 less clock cycles for the column access time) and 1 clock cycle to return a word. Assuming that each word is in a different DRAM row, calculate the bandwidth of the system in byte per clock cycles (bandwidth = number of bytes per clock cycles) for the transfer of one block from Main Memory to Cache Memory (not interleaved memory system). Provide the solution with at least 2 decimals
Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?
The overhead required to read an entry in a page table (including the time to access TIB) is 60 nanoseconds. To reduce this overhead, the computer has a TIB that can hold 16 entries and be accessed in 10 nanoseconds.a) Let B = TLB lookup time, T - memory cycle time, and p = hit ratio. Finda formula that expresses the effective access time.b) What hit ratio is needed to reduce the effective access time to 70 nanoseconds?