e t n Se 11• RECAssume a very simple microprocessor with 12 address lines with which wewish to implement only a quarter of the largest addressable memoryusing the same 512x8 memory chips. Physical memory must be placed onthe upper half of the memory map.a. What is the size of the memory implemented?b. How many memory chips would be needed to implement thismemory space?c. How many lines would each chip require to address its internalmemory cells?d. How many lines would be required to select each chipe. Draw a simplified partial address decoding table listing all thememory chips as (MEMO, MEM1, MEM 2. etc.) and show the linesused for address decoding (chip selection) and those used to addressinternal memory cells. Fill the table appropriately with 1's, O's and X's(don't cares).4. Consider the data definition statement below.num1 WORD 192AHarray1 WORD OA23BH, 7EA1H, 5BEFHa. Write assembly code to compute the size of the data label array1.b. Write assembly code to add the second element of array1 to

as our policy i am solving first three parts

(2 Assume a very simple microprocessor with 12 address lines with which we wish to implement only a quarter of the largest addressable memory using the same 512x8 memory chips. Physical memory must be placed on the upper half of the memory map. a. What is the size of the memory implemented? b. How many memory chips would be needed to implement this memory space? c. How many lines would each chip require to address its internal memory cells?

(2 Assume a very simple microprocessor with 12 address lines with which we wish to implement only a quarter of the largest addressable memory using the same 512x8 memory chips. Physical memory must be placed on the upper half of the memory map. a. What is the size of the memory implemented? b. How many memory chips would be needed to implement this memory space? c. How many lines would each chip require to address its internal memory cells?

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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Suppose we have 1G × 16 RAM chips that make up a 32G × 64 memory that uses high interleaving. (Note: This means that each word is 64 bits in size and there are 32G of these words.)1. a) How many RAM chips are necessary?2. b) Assuming four chips per bank, how many banks are required?3. c) How many lines must go to each chip?4. d) How many bits are needed for a memory address, assuming it is word addressable?5. e) For the bits in part d, draw a diagram indicating how many and which bits are used for chip select, and how many and which bits are used for the address on the chip.6. f) Redo this problem assuming that low-order interleaving is being used instead.
A given computer has a single cache memory (off-chip) with a 2 ns hit time and a 98% hit rate. Its main memory has 40 ns access time. i. What is the computer’s effective access time?ii. If an on-chip cache with a 0.5 ns hit time and a 94% hit rate is added to it, what is the computer’s new effective access time?iii. How much of a speedup does the on-chip cache give the computer?
(a) How many bits are actually in a 1-Mb memorychip? In a 4-Gb chip? (b) Howmany 128-Kb blocksmust be replicated to form the 256-Mb memory inFig.?
Consider two microprocessors having 8-bit and 16-bit wide external data buses, respectfully. The two processors are identical otherwise and their bus cycles are the same speed. Suppose all instructions and operands are two Bytes. By what factor do the maximum data transfer rates vary? Suppose all instructions and operands are one Byte. By what factor do the maximum data transfer rates vary? Discuss your answers.
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Assume SS=5000H, DS=6000H, ES=7000H, CS=9000H, BX=1000H, DI=2000H, BP=3000H, IP=4000H, SI=2000H, the physical address and the addressing mode of the following memory location specified in the instruction MOV [DI+3000H], AL are ……… and ……… .
You buy a ROM memory chip that is 64Kx8. How many memory address lines does the chip have? A 16 B 64K C 512 D 8
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answer: If a memory of 0.5K bytes is connected to 8085 MP, Then the number of lower order address lines required are -------lines, and if 2 higher order address lines are considered as don't care lines,then a fold back space is exists and equals .to----bytes
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