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2) The circuit below shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differential pair, while the current source transistors Q4 and Qs form the active loads for Q1 and Q2, respectively. The DC bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Qz is not shown. It is required to design the circuit to meet the following specifications (a) Differential gain Ad= 80 V/V. (b) IREF = 1 = 100 µA. (c) The DC voltage at the gates of Q6 and Q3 is + 1.5 V (d) The DC voltage at the gates of Q7, Q4, and Qs is -1 V +2.5 V The technology available is specified as follows: HCOX = 3µ,Cox = 90 µA/N²; Vtn = I Vtpl = 0.7 V, VA = IVael = 20V. Specify the required value of R and the WIL ratios for all transistors. Also specify Ip and |VGs| at which each transistor is operating. For DC bias calculations you may

2) The circuit below shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differential pair, while the current source transistors Q4 and Qs form the active loads for Q1 and Q2, respectively. The DC bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Qz is not shown. It is required to design the circuit to meet the following specifications (a) Differential gain Ad= 80 V/V. (b) IREF = 1 = 100 µA. (c) The DC voltage at the gates of Q6 and Q3 is + 1.5 V (d) The DC voltage at the gates of Q7, Q4, and Qs is -1 V +2.5 V The technology available is specified as follows: HCOX = 3µ,Cox = 90 µA/N²; Vtn = I Vtpl = 0.7 V, VA = IVael = 20V. Specify the required value of R and the WIL ratios for all transistors. Also specify Ip and |VGs| at which each transistor is operating. For DC bias calculations you may

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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2) The circuit below shows a circuit for a differential amplifier with an active load. Here Qi and Q2 form the differential pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2, respectively. The DC bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. It is required to design the circuit to meet the following specifications (a) Differential gain Ad= 80 V/V. (b) IREF = | = 100 HA. (c) The DC voltage at the gates of Q6 and Q3 is + 1.5 V (d) The DC voltage at the gates of Q7, Q4, and Qs is -1 V +2.5 V The technology available is specified as follows: HCox = 3µ,Cox = 90 HA/V²; Vta = 1 Vtel = 0.7 V, KAr = I Kael = 20V. Specify the required value of R and the WIL ratios for all transistors. Also specify Ip and |VGs| at which each transistor is operating. For DC bias calculations you may IREFY neglect channel-length modulation. Note: The input to Q2 is not readable (it should be -Via/2) Os -2.5 V
Transcribed Image Text:2) The circuit below shows a circuit for a differential amplifier with an active load. Here Qi and Q2 form the differential pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2, respectively. The DC bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. It is required to design the circuit to meet the following specifications (a) Differential gain Ad= 80 V/V. (b) IREF = | = 100 HA. (c) The DC voltage at the gates of Q6 and Q3 is + 1.5 V (d) The DC voltage at the gates of Q7, Q4, and Qs is -1 V +2.5 V The technology available is specified as follows: HCox = 3µ,Cox = 90 HA/V²; Vta = 1 Vtel = 0.7 V, KAr = I Kael = 20V. Specify the required value of R and the WIL ratios for all transistors. Also specify Ip and |VGs| at which each transistor is operating. For DC bias calculations you may IREFY neglect channel-length modulation. Note: The input to Q2 is not readable (it should be -Via/2) Os -2.5 V
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