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2. An N-bit Johnson counter consists of an N-bit shift register with a reset signal. The output of the shift register (Sout) is inverted and fed back to the input (Sin). When the counter is reset, all of the bits are cleared to 0. (a) Show the sequence of outputs, Q3:0, produced by a 4-bit Johnson counter starting immediately after the counter is reset. (b) How many cycles elapse until an N-bit Johnson counter repeats its sequence? Explain. (c) Design a decimal counter using a 5-bit Johnson counter, ten AND gates, and inverters. The decimal counter has a clock, a reset, and ten one-hot outputs Y9:0- When the counter is reset, Yo is asserted. On each subsequent cycle, the next output should be asserted. After ten cycles, the counter should repeat. Sketch a schematic of the decimal counter. (d) What advantages might a Johnson counter have over a conventional counter?

2. An N-bit Johnson counter consists of an N-bit shift register with a reset signal. The output of the shift register (Sout) is inverted and fed back to the input (Sin). When the counter is reset, all of the bits are cleared to 0. (a) Show the sequence of outputs, Q3:0, produced by a 4-bit Johnson counter starting immediately after the counter is reset. (b) How many cycles elapse until an N-bit Johnson counter repeats its sequence? Explain. (c) Design a decimal counter using a 5-bit Johnson counter, ten AND gates, and inverters. The decimal counter has a clock, a reset, and ten one-hot outputs Y9:0- When the counter is reset, Yo is asserted. On each subsequent cycle, the next output should be asserted. After ten cycles, the counter should repeat. Sketch a schematic of the decimal counter. (d) What advantages might a Johnson counter have over a conventional counter?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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2. An N-bit Johnson counter consists of an N-bit shift register with a reset signal. The output of the shift register (Sout) is inverted and fed back to the input (Sin). When the counter is reset, all of the bits are cleared to 0. (a) Show the sequence of outputs, Q3:0, produced by a 4-bit Johnson counter starting immediately after the counter is reset. (b) How many cycles elapse until an N-bit Johnson counter repeats its sequence? Explain. (c) Design a decimal counter using a 5-bit Johnson counter, ten AND gates, and inverters. The decimal counter has a clock, a reset, and ten one-hot outputs Y9:0. When the counter is reset, Yo is asserted. On each subsequent cycle, the next output should be asserted. After ten cycles, the counter should repeat. Sketch a schematic of the decimal counter. (d) What advantages might a Johnson counter have over a conventional counter?
Transcribed Image Text:2. An N-bit Johnson counter consists of an N-bit shift register with a reset signal. The output of the shift register (Sout) is inverted and fed back to the input (Sin). When the counter is reset, all of the bits are cleared to 0. (a) Show the sequence of outputs, Q3:0, produced by a 4-bit Johnson counter starting immediately after the counter is reset. (b) How many cycles elapse until an N-bit Johnson counter repeats its sequence? Explain. (c) Design a decimal counter using a 5-bit Johnson counter, ten AND gates, and inverters. The decimal counter has a clock, a reset, and ten one-hot outputs Y9:0. When the counter is reset, Yo is asserted. On each subsequent cycle, the next output should be asserted. After ten cycles, the counter should repeat. Sketch a schematic of the decimal counter. (d) What advantages might a Johnson counter have over a conventional counter?
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