2. You have to design a vending machine for a 4 Tk product. The vending machine can only accept inputs: no money (can be represented as input w=00), Tk 1 (can be represented as input w=01), and Tk 3 (can be represented as input w=10). Once an acceptable input is more than or equal to 4 Tk, the machine immediately generates an output Q=1, goes back to the initial state, and gives back the change (if required). Change in Tk is represented as 2 digit binary output c={c1c2}. Output c has to be calculated

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2. You have to design a vending machine
for a 4 Tk product. The vending machine
can only accept inputs: no money (can be
represented as input w=00), Tk 1 (can be
represented as input w=01), and Tk 3
(can be represented as input w=10).
Once an acceptable input is more than or
equal to 4 Tk, the machine immediately
generates an output Q=1, goes back to
the initial state, and gives back the
change (if required). Change in Tk is
represented as 2 digit binary output
c={c1c2}. Output c has to be calculated
and initialized. Suppose, changes are
1Tk, 2Tk (assumed). Initialize 1Tk as
c=00
and
2Tk
as
c=01. Reset
functionality is not mandatory. Draw the
state diagram, the state-assigned table,
write the Verilog code, run simulations
and verify your answer.
t t t t. t. t. t t. t. t. t. t.
1 3 0310| 3 | 3 0|3 |0
00 01 10 00 10 01 00 10 10 00 10 00
010|010 0
clock
Tk input
10 | 01
1
0|00
?
?
?
?
?
?
?
?
?
?
?
Expected Output:
The timing diagram should contain
waveforms as described in the table. The
clock period should be 10 ns. The
discussion must contain a state diagram,
state
assigned
table,
and
brief
explanations of all high output situations
e.g. Q
|high during t3, to, and to clock
cycles. Briefly explain these situations in
light of the problem statement and your
derived state diagram/state assigned
table. Also, initialize and complete output
С.
Transcribed Image Text:2. You have to design a vending machine for a 4 Tk product. The vending machine can only accept inputs: no money (can be represented as input w=00), Tk 1 (can be represented as input w=01), and Tk 3 (can be represented as input w=10). Once an acceptable input is more than or equal to 4 Tk, the machine immediately generates an output Q=1, goes back to the initial state, and gives back the change (if required). Change in Tk is represented as 2 digit binary output c={c1c2}. Output c has to be calculated and initialized. Suppose, changes are 1Tk, 2Tk (assumed). Initialize 1Tk as c=00 and 2Tk as c=01. Reset functionality is not mandatory. Draw the state diagram, the state-assigned table, write the Verilog code, run simulations and verify your answer. t t t t. t. t. t t. t. t. t. t. 1 3 0310| 3 | 3 0|3 |0 00 01 10 00 10 01 00 10 10 00 10 00 010|010 0 clock Tk input 10 | 01 1 0|00 ? ? ? ? ? ? ? ? ? ? ? Expected Output: The timing diagram should contain waveforms as described in the table. The clock period should be 10 ns. The discussion must contain a state diagram, state assigned table, and brief explanations of all high output situations e.g. Q |high during t3, to, and to clock cycles. Briefly explain these situations in light of the problem statement and your derived state diagram/state assigned table. Also, initialize and complete output С.
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