3) Suppose an application program requires 2500H bytes of memory for its code, 2FOH bytes of memory for its data, and 2A0H bytes of memory for its stack. Shows how this application is positioned in a memory with a 20-bit address bus if locations 00000H to 0A000H is reserved for the operating system (OS) softtware.

3) Suppose an application program requires 2500H bytes of memory for its code, 2FOH bytes of memory for its data, and 2A0H bytes of memory for its stack. Shows how this application is positioned in a memory with a 20-bit address bus if locations 00000H to 0A000H is reserved for the operating system (OS) softtware.

Name: theoneratinn3) Suppose an application program requires 2500H bytes of
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Description: theoneratinn3) Suppose an application program requires 2500H bytes of memory for its code,2FOH bytes of memory for its data, and 2A0H bytes of memory for its stack.Shows how this application is positioned in a memory with a 20-bit address bus ifloca

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 21VE

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instruction is in the first picture please give me only implementation of int L1lookup(u_int32_t address) and int L2lookup(u_int32_t address) cacheSim.h #include<stdlib.h>#include<stdio.h>#define DRAM_SIZE 1048576typedef struct cb_struct {unsigned char data[16]; // One cache block is 16 bytes.u_int32_t tag;u_int32_t timeStamp; /// This is used to determine what to evict. You can update the timestamp using cycles.}cacheBlock;typedef struct access {int readWrite; // 0 for read, 1 for writeu_int32_t address;u_int32_t data; // If this is a read access, value here is 0}cacheAccess;// This is our dummy DRAM. You can initialize this in anyway you want to test.unsigned char * DRAM;cacheBlock L1_cache[2][2]; // Our 2-way, 64 byte cachecacheBlock L2_cache[4][4]; // Our 4-way, 256 byte cache// Trace points to a series of cache accesses.FILE *trace;long cycles;void init_DRAM();// This function print the content of the cache in the following format for an N-way cache with M Sets// Set 0…
Code a descriptor that describes a data memory segment that grows upward and begins at location 03000000H and ends at location 05FFFFFFH and can be written. The memory has not been accessed, and can be accessed with the lowest privilege level. Assume that the segment is available (i.e., AV=1) and that the instructions are 32 bits (i.e., D=1).
A direct-mapped cache consists of 8 blocks. A byte-addressable main memory contains 4K blocks of eight bytes each. Access time for the cache is 20 ns and the time required to fill a cache slot from main memory is 300 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. c) Compute the effective access time for this program. Show me how to solve using this equation: EAT = H x AccessC + (1 – H) x AccessMM where H is the cache hit rate and AccessC and AccessMM are the access times for cache and main memory, respectively. thanks
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Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. Could you hand draw the page table, if possible a) Suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) b) What is the size of the two-level page table
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Memory Hierarchy and Cache Suppose that we have a computer that uses a memory address of 12-bits. This computer has a 64-byte cache with 16 bytes per frame. The computer accesses a number of memory locations throughout the course of a running program. Suppose this computer uses direct-mapped cache. The system accesses the following memory addresses (given in hex) in this exact order: F2E, A17, 2E0, 44E, 34F, 341, B50, B58 a. What is the hit ratio for the memory reference sequence given above? b. Show the content of each cache frame following each memory reference (frame content to be shown as tag +frame index) c.If we keep the same cache size and the same frame size but switch to a 2-way set associative cache mapping scheme. Given the memory address reference 555, indicate where we would look in the cache to find this data. Indicate which fields will be used to find the exact location?