Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes.   a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?

For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.Tag            Index     Offset31–10          9–5        4–01. What is the cache block size (in words)?2. How many entries does the cache have?3. What is the ratio between total bits required for such a cache implementation over the data storage bits?Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 How many blocks are replaced? What is the hit ratio? List the fi nal state of the cache, with each valid entry represented as a record of <index, tag, data>

The following data segment starts at memory address 1000h (hexadecimal) .data printString        BYTE   "ASSEMBLY IS FUN",0 moreBytes       BYTE  25(DUP)0 dateIssued      DWORD   ? dueDate           DWORD   ? elapsedTime    Word     ? What is the hexadecimal address of dueDate ?  a. 1045h b. 1029h c.1010h d. 102Dh

4. The figure below shows an 8-way interleaved, byte-addressable memory. The total size of the memory is 4 KB. The elements A[i]G) of a 2-dimensional array A are 4-bytes (one-word) in length and can be stored in the memory as shown, where 0 < ij <7. The width of the bus between CPU and memory is 32 bits, that is, it can carry only one word at a time. Bank 1 Bank 7 Bank 0 31 7 A[7][0] A[I][0] A[0]|0] 32 A[7]1] 64 A[7]|2] A[I][2] A[0||2] RANKO 255 224 AI기기 A[I][7] A[0||7) RANKN ...... Since the address space of the memory is 4 KB, 12 bits are needed to uniquely identify each memory location, i.e., Addr[11:0]. Find out and explain which bits of the address will be used for: • Byte on bus: Addr […... :...] Bank index bits within a bank: Addr [.... .] • Chip select address bits within a rank: Addr […... .] • Rank bits: Addr […... :....]

Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? 8 bits each. With this system, what’s the maximum number of pages that a process can have? 256 Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? 1024 Bytes Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number. DONE Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert…

Part A For each byte sequence listed, determine the Y86 instruction sequence it encodes. If there is some invalid byte in the sequence, show the instruction sequence up to that point and indicate where the invalid value occurs. For each sequence, the starting address, then a colon, and then the byte sequence are shown. 0x100: 30f3fcfffff40630008000000000000 0x100: 30f3fcfffffff irmovq $-4,%rbx Ox10a: 40630008000000000000 | rrmovq %rsi,0×80A(%rcx) O0x115: 00 halt Ox100: 30f3fcffffffff irmovq $-4,%rbx Ox10a: 40630008000000000000 | rmmovq %rsi,0x800(%rbx) Ox114: 00 halt 0x100: 30f3fcfffffffff rrmovq $-8,%rbx Ox109: 40630008000000000000 | rmmovq %rsi,0x800(%rbx) 0x200: a06f800c020000000000000030f30a00000000000000 0x113: 00 halt 0x100: 30f3fcffffffffff irmovq $-4,%rbx 0x200: a06f pushq %rsi 0x10a: 40630008000000000000 | rmmovq %rsi,0x800(%rbx) Ox202: 800c02000000000000 call proc Ox116: 00 halt 0x20b: 00 halt 0x20c: proc: Submit Request Answer 0x20c: 30f30a00000000000000 | irmovq $10,%rbx…

CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers:  (a)  How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate  (b)  Repeat the above for the index field. (c)  Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.

I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?

In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.

Fill in blank Suppose that linear page table is used where the memory addresses are 12-bit binary numbers and the page size is 256 bytes. If a virtual address in binary format is 101000011100, then the VPN (virtual page number) in binary format will be ---------