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- Recall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 1. Buff ers are employed between diff erent levels of memory hierarchy to reduce access latency. For this given confi guration, list the possible buff ers needed between L1 and L2 caches, as well as L2 cache and memory.2. Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.3. For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), confi guration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.Consider the following program and cache behaviors. Data Reads per1000 Instructions Data Writes per1000 Instructions Instruction…Q3 If a microprocessor has L1 and L2 caches. The access time for L1 cache is τ. The miss penalties for transferring a block of memory from L2 to L1 is 10τ and it takes 120τ for transferring a block from memory to L2. The hit rates are the same for instructions and data and that the hit rates in the L1 and L2 caches are 0.90 and 0.85, repectively. I. Determine the fraction of accesses miss in both the L1 and L2 caches, thus requiring access to the main memory? II. What is the average access time as seen by the processor? Q4 Determine the number of bytes included in the address ranging from 123000H to 0C37000H, you must present the answers using units of Mbytes, Kbytes and bytes. Q5 If the size of a program is 424892 Bytes and its starting address is 000000H, determine the ending address of the program.A cache memory has a line size of eight 64-bit words and a capacity of 4K words. The main memory size that is cacheable is 1024 Mbits. Assuming 4-way set associative mapping and that the addressing is done at the byte level. What is the format of the main memory addresses (i.e s-d, d, and w)? For the hexadecimal main memory location 2BFACEDH, find the corresponding 4-way set-associative memory format
- In this exercise, we will look at the diff erent ways capacity aff ects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. Th e following table shows data for L1 caches attached to each of two processors, P1 and P2. L1 Size L1 Miss Rate L1 Hit Time P1 2 KiB 8.0% 0.66 ns P2 4 KiB 6.0% 0.90 ns Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates? What is the Average Memory Access Time for P1 and P2? Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?Q.A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine that the block is missing and bring it into cache.) Assume that a request is always started in parallel to both cache and to main memory (so if it is not found in cache, we do not have to add this cache search time to the memory access). If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty.Q.) Compute the hit ratio for a program that loops four times from addresses 0x0 to 0x43 in memory.Q.A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine that the block is missing and bring it into cache.) Assume that a request is always started in parallel to both cache and to main memory (so if it is not found in cache, we do not have to add this cache search time to the memory access). If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty.Q.) Show the main memory address format, which allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes.
- Q.Assuming a 2-way set-associative cache What does cache look like after the 10 memory accesses have taken place?CA_7 Let a program use 5 contiguous words and loop these words 100 times (meaning the execution trace of this program is [012340123401234...1. Furthermore, let a cache have 4 word-sized blocks. How many misses will there be if the cache is: (a)Direct mapped? (b) Fully-associative with commonly used Least-Recently-Used replacement? (c) Fully-associative with less well-known Most-Recently-Used replacement? (d) Set-associative with two sets and uses first-in-first-out replacement? (e) Set-associative with two sets and uses first-in-last-out replacement?Ifthere is a 64K cache with a block size of 7k, what is the number of bits in the indes field of block address, given the cache is (3) F Associative, (b) Direct Mapped, (¢) 2-way Sct Associative, and ) 4 - way Set Associative. b
- 6 Recall that we have two write policies and two write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 6.1 Buffers are employed between different levels of memory hierarchy to reduce access latency. For this given configuration, list the possible buffers needed between L1 and L2 caches, as well as L2 cache and memory. 6.2 Describe the procedure of handling an L1 write-miss, considering the components involved and the possibility of replacing a dirty block. 6.3 For a multilevel exclusive cache con guration (a block can only reside in one of the L1 and L2 caches), describe the procedures of handling an L1 write-miss and an L1 read-miss, considering the components involved and the possibility of replacing a dirty block.3) Assume that there is a cache with 4 blocks and the block size is 1 byte (in total only 4B cache). The cache is initially empty. For two different configurations of the cache; direct-mapped and 2-way set associative, given memory addresses are accessed in the given order. Write if given addresses are hit or miss in the cache. address: 3 - 11 - 0 - 3 - 11Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 13 bits wide.The cache is 4-way set associative (E = 4), with a 4-byte block size(B = 4) and eight sets (S = 8).Consider the following cache state. All addresses, tags, and valuesare given in hexadecimal format. The Index column contains the set index for each set of four lines. The Tag columns contain the tag value for each line. The V columns contain the valid bit for each line. The Bytes 0−3 columns contain the data for each line, numbered left to right starting with byte 0 on the left. A. What is the size (C) of this cache in bytes?B. The box that follows shows the format of an address (1 bit perbox). Indicate (by labeling the diagram) the fields that would beused to determine the following:CO. The cache block offsetCI. The cache set indexCT. The cache tag