If a microprocessor has L1 and L2 caches. The access time for L1 cache is τ. The miss penalties for transferring a block of memory from L2 to L1 is 10τ and it takes 120τ for transferring a block from memory to L2. The hit rates are the same for instructions and data and that the hit rates in the L1 and L2 caches are 0.90 and 0.85, repectively. I. Determine the fraction of accesses miss in both the L1 and L2 caches, thus requiring access to the main memory? II. What is the average access time as seen by the processor?

If a microprocessor has L1 and L2 caches. The access time for L1 cache is τ. The miss penalties for transferring a block of memory from L2 to L1 is 10τ and it takes 120τ for transferring a block from memory to L2. The hit rates are the same for instructions and data and that the hit rates in the L1 and L2 caches are 0.90 and 0.85, repectively. I. Determine the fraction of accesses miss in both the L1 and L2 caches, thus requiring access to the main memory? II. What is the average access time as seen by the processor?

Name: Q3If a microprocessor has L1 and L2 caches. The access time for L1 cac
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Description: Q3If a microprocessor has L1 and L2 caches. The access time for L1 cache is τ. The miss penalties for transferring a block of memory from L2 to L1 is 10τ and it takes 120τ for transferring a block from memory to L2. The hit rates are the same for ins

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 3PE: Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one...

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