4. A generic sequential circuit is given below. The circuit's inputs are A, CLK and CLR and output is Y. The propagation delay of flip-flops (tclk q) is 50ps, tsetup and thold time requirements are 50ps and 25ps respectively. Clock signal (CLK) has the clock skew value of 10ps. (ps = picosecond, 101² second, GHz= Gigahertz, 10° Hertz) D. CLR Clock Skew CLK CLR i. Assume that the delay of each combinational logic gate is calculated as d = number of inputsx25ps.Calculate the propagation delay for the combinational part of the circuit given in figure. Find the critical (largest delay) path for combinational part of the given circuit. ii. Calculate the minimum cycle time and the maximum frequency at which the circuit can оperate. Calculate the setup time slack when the circuit operates at 4.0GHZ frequency. In order to have +50ps setup time slack, what should be the operating frequency of circuit? iii.

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4. A generic sequential circuit is given below. The circuit's inputs are A, CLK and CLR and output
is Y. The propagation delay of flip-flops (tcLK Q) is 50ps, tsetup and thold time requirements are 50ps
and 25ps respectively. Clock signal (CLK) has the clock skew value of 10ps.
(ps = picosecond, 10-12 second, GHz= Gigahertz, 10° Hertz)
CLB
CLR
Clock Skew
CLK
CLR
i.
Assume that the delay of each combinational logic gate is calculated as d = number of
inputsx25ps.Calculate the propagation delay for the combinational part of the circuit
given in figure. Find the critical (largest delay) path for combinational part of the given
circuit.
ii.
Calculate the minimum cycle time and the maximum frequency at which the circuit can
operate.
Calculate the setup time slack when the circuit operates at 4.0GHZ frequency. In order to
ji.
have +50ps setup time slack, what should be the operating frequency of circuit?
Calculate the hold time slack when the circuit operates at 4.0GHZ frequency.
iv.
Transcribed Image Text:4. A generic sequential circuit is given below. The circuit's inputs are A, CLK and CLR and output is Y. The propagation delay of flip-flops (tcLK Q) is 50ps, tsetup and thold time requirements are 50ps and 25ps respectively. Clock signal (CLK) has the clock skew value of 10ps. (ps = picosecond, 10-12 second, GHz= Gigahertz, 10° Hertz) CLB CLR Clock Skew CLK CLR i. Assume that the delay of each combinational logic gate is calculated as d = number of inputsx25ps.Calculate the propagation delay for the combinational part of the circuit given in figure. Find the critical (largest delay) path for combinational part of the given circuit. ii. Calculate the minimum cycle time and the maximum frequency at which the circuit can operate. Calculate the setup time slack when the circuit operates at 4.0GHZ frequency. In order to ji. have +50ps setup time slack, what should be the operating frequency of circuit? Calculate the hold time slack when the circuit operates at 4.0GHZ frequency. iv.
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