4.16 In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250 ps 350 ps 150 ps 300 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: ALU/Logic Jump/Branch LDUR STUR 45% 20% 20% 15%

4.16 In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250 ps 350 ps 150 ps 300 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: ALU/Logic Jump/Branch LDUR STUR 45% 20% 20% 15%

C++ for Engineers and Scientists

4th Edition

ISBN:9781133187844

Author:Bronson, Gary J.

Publisher:Bronson, Gary J.

Chapter2: Problem Solving Using C++using

Section2.3: Data Types

Problem 9E: (Practice) Although the total number of bytes varies from computer to computer, memory sizes of...

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In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which theprocessor fetches the following instruction word: 10101100100001010000000000011100 Assume that the data memory is all zeros and that the processor’s registers havethe following values at the beginning of the cycle in which the above instructionword is fetched: R0 R1 R2 R3 R4 R5 R6 R8 R12 R31 0 2 4 6 13 10 12 16 24 31 a. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the topof the following Figure) for this instruction word? (Pic3) b. What are the values of ALU control unit’s inputs (ALUOp and Instruction[5-0])for this instruction? c. What is the new PC address after this instruction is executed? Highlight the paththrough which this value is determined. d. For the ALU and the two add units, what are their data input values? ALU Add (PC+4) Add…
10. Consider the following code: .386 .model flat, stdcall .stack 4096 ExitProcess PROTO, dwExitCode : DWORD .data aVal SDWORD -6 bVal SWORD 19h cVal DWORD 17h .code mov edx, aVal add edx, edx mov eax, 0FFFFFFFFh mov ax, bVal sub edx, eax Show the content of edx and eax after executing each instruction in Hexadecima
4.19.16: [5] <COD §4.6>. In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: Also, assume that instructions executed by the processor are broken down as follows: (a) What is the clock cycle time in a pipelined and non-pipelined processor? (b) What is the total latency of an lw instruction in a pipelined and non-pipelined processor? (c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (d) Assuming there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? No hand written and fast answer with explanation
Considering the following contents of Stack Segment (SS) Register and Stack Pointer (SP) Register: SS = A5B0H, SP = 4DF0H (a) Calculate the values of Top of Stack (ToS) and Bottom of Stack (BoS)? (b) Consider the following operations on the stack: PUSH AX PUSH [CX] PUSH 10 POP [BX] POP AX What is the value of ToS after all these operations? Also, provide the value of ToS after each instruction.
We will explore the impact of cache capacity on performance, focusing exclusively on the data cache and excluding instruction storage in the caches. Cache access time is directly linked to its capacity. For the sake of simplicity, let's assume that accessing the main memory takes 100ns, and in a specific program, 50% of instructions involve data access. Two distinct processors, denoted as P1 and P2, are engaged in executing this program. Each processor is equipped with its own L1 cache. L1 size L1 Miss Rate L1 Hit Time P1 64 KB 3.6% 1.26 ns P2 128 KB 3.1% 2.17ns (a) What is the AMAT for P1 and P2 assuming no other levels of cache?
17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
In this exercise we compare the performance of 1-issue and 2-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution. Problems in this exercise refer to the following loop(written in C):for(i=0;i!=j;i+=2)b[i]=a[i]–a[i+1];When writing MIPS code, assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else. i j a b c Free R5 R6 R1 R2 R3 R10,R11,R12 Translate this C code into MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance.
Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?
Consider the following instruction:Instruction: Add Rd, Rs, RtInterperation: Reg[Rd] = Reg[Rs] + Reg[Rt] RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a, What are the values of control signals generated by the control in Figure 4.2 for the above instruction? b, Which resources (blocks) perform a useful function for this instruction? c, Which resources (blocks) produce outputs, but their outputs are not used for this instruction? d, which resources (blocks) produce no output for this instruction?
Write MIPS assembly for the following function. Assume N is passed to yourfunction in register $a0. Your output should be in register $v0 at the end of yourfunction. Note: You must implement this function recursively. The purpose of thisassignment is to learn how to manipulate the stack correctly in MIPS. int Myfun (int N){ if (N<3) return 1; return ( 2* Myfun(N-1)+ Myfun(N-2));}Please explain each instruction with a comment. Please submit your source codeand a screenshot that shows the registers with correct output value for N=3, i.e.,Myfun(3) returns 3 and Myfun(4) returns 7
Q1: Suppose the hypothetical processor has two I/O instructions: (3+3+3)0011=Load AC from I/O0111=Store AC to I/OIn this case, the 12-bit address identifies a particular external device. Show the program execution using figure for the following program:a) Load AC from device 6b) Add contents of memory location 880c) Store AC to device 7 (Note: Question is to be solved similar to the pictures attached with minimum explaination of a line or two with the steps and SHOULD include the memory location 880 as stated in the question)
In this exercise, we examine in detail how much an instruction is executed in a single-cycle Datapath. The problem refers to a clock cycle in which the processor fetches the following instruction word: 1010 1100 0110 0010 0000 0000 0001 0100. Assume that data memory is all zeros and that the processor's registers have the following values at the beginning of the cycle in which of the instruction word is fetched: (See image attached) What is the new PC address after this instruction is executed? Highlight the path through which this value is determined?