88 microprocessor sys - How many clocks is i- Find the memory cyc ii- Draw the Read men
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- How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?Most Intel CPUs use the __________, in which each memory address is represented by two integers.A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.
- The time it takes to perform the fetch instruction and decode instruction steps is called the execution time. True or false?Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?For a microprocessor, if the total time of all positive cycles in 5 seconds is 2 seconds, and the Off time in every cycle is 0.335µs, (i) What is the frequency of its clock? (ii) What is the time taken to reset the microprocessor?
- A given computer has a single cache memory (off-chip) with a 2 ns hit time and a 98% hitrate. Its main memory has 40 ns access time. What is the computer’s effective access time? If an on-chip cache with a 0.5 ns hit time and a 94% hit rate is added to it, what isthe computer’s new effective access time? How much of a speedup does the on-chip cache give the computer?Suppose that A 8051 family CPU with 8K bytes on-chip ROM, please give the ROM memory address (6’). Also please give the initial address location and the maximum address location of 8051 family CPU (6’).On a uniprocessor, portion A of program P consumes 24 seconds, while portion B consumes 822 seconds. On a parallel computer, moderately serial portion A speeds up 4 times, while perfectly parallel portion B speeds up by the number of processors. 1- What is the speedup of program P on 1,024 processors? _______ times 2- How many processors are required to achieve at least half the theoretical maximum possible speedup on P?
- in 80886 microprocessor Suppose that. DS = 0200H, BX = 0300H, and DI-400H Determine the memory address accessed by each of the following instructions, assuming real mode operation: (1) MOV AL,[1234H] (2) MOV AX,[BX] (3) MOV [DI]ALWhen we already have RAM (Random Access Memory), which is often referred to as a volatile memory, why do we need cache memory?Transistors are used in both cache memory and random access memory (RAM). Is it possible to use the same kind of memory for every part of a computer's operation?CPUs with either a synchronous or asynchronous memory bus are preferable. Thanks. The way you arrived at this conclusion needs explaining.