You must show all work for every problem that requires it.The point values for problems may be changed at the professor's discretion. Read each question carefully and follow the instructions. A computer hardware as the following latency for its instructions in Pico seconds:TypeInstruction MemoryRegister ReadALU OperationData MemoryRegister WriteTotalR-Format250150200020620lw25015020025020870sw2501502002500850beq25015020000600J2500000250 For a single-cycle implementation what Clock Rate does the machine needs to operate at? For a multi-cycle implementation what Clock Rate does the machine needs to operate at? Provide the type, assembly language instruction and binary representation of instructions described by the following MIPS fields:Op=0x0, rs=3, rt=2, rd=3, shamt=0, funct=34Op=0x23, rs=3, rt=1, const=0x4 In the snippet of assembly code below, how many times is instruction memory accessed? How many times is data memory accessed? (Count only accesses to memory, not registers.) lw $v1, 0($a0) addi $v0, $v0, 1sw $v1, 0($a1) addi $a0, $a0, 1 Consider the following instruction:SW Rt , Rd(Rs)Interpretation: Reg[Rt] = Mem[Reg[Rd] + Reg[Rs]] What are the values of the control signals generated by the control in the fig above?RegDestJumpBranchMemReadMemtoRegALUopMemWriteALUSrcRegWrite Highlight the Datapath that would be used in an ADD Immediate instructionExample: ADDI s0, s0, Imm List and describe the stages of the classical MIPS pipeline? Consider a 10 billion instruction program, consisting of 20% loads, 20% stores, and 60% other instructions. Will this program run faster on processor A or processor B?Processor A: A 200 MHz single cycle processor.Processor B: A 1000MHz multi-cycle processor on whichloads take 10 cycles;stores take 8 cycles; andall other instructions take 4 cycles. How many cycles are required to run the following code on a Single cycle MIPS processor? Calculate the CPI of the program?ADDI $t1, $t1, 1ADDI $t2, $t2, 4ADDI $s0, $0, 16while: BEQ $s0, $0, DoneADDI $s0, $s0, -1J whileDone How many cycles are required to run the following code on a multicycle MIPS processor? Calculate the CPI of the program?ADDI $s0, $0, 5while: BEQ $s0, $s0, DoneADDI $s0, $s0, -1J whileDone: Please list and define the three types of pipeline hazards that exist. Also, for each of the hazards, list at least one method of reducing the number of occurrences of the hazard. For the code sequence below, state whether it must stall, can avoid stalls using only forwarding, or can execute without stalling or forwarding.i1: addi $t1, $t0, 1 i2: addi $t2, $t1, 2i3: addi $t3, $t0, 2 i4: addi $t4, $t0, 4 i5: addi $t4, $t3, -1 i6: beq $t0, $0, end end:Which lines in the program would require stalls based on data dependenciesReorder the program so that no stalls are required.

Question

You must show all work for every problem that requires it.The point values for problems may be changed at the professor's discretion. Read each question carefully and follow the instructions.     A computer hardware as the following latency for its instructions in Pico seconds:TypeInstruction MemoryRegister ReadALU OperationData MemoryRegister WriteTotalR-Format250150200020620lw25015020025020870sw2501502002500850beq25015020000600J2500000250 For a single-cycle implementation what Clock Rate does the machine needs to operate at? For a multi-cycle implementation what Clock Rate does the machine needs to operate at?              Provide the type, assembly language instruction and binary representation of instructions described by the following MIPS fields:Op=0x0, rs=3, rt=2, rd=3, shamt=0, funct=34Op=0x23, rs=3, rt=1, const=0x4    In the snippet of assembly code below, how many times is instruction memory accessed? How many times is data memory accessed? (Count only accesses to memory, not registers.) lw $v1, 0($a0) addi $v0, $v0, 1sw $v1, 0($a1) addi $a0, $a0, 1                  Consider the following instruction:SW Rt , Rd(Rs)Interpretation: Reg[Rt] = Mem[Reg[Rd] + Reg[Rs]] What are the values of the control signals generated by the control in the fig above?RegDestJumpBranchMemReadMemtoRegALUopMemWriteALUSrcRegWrite                   Highlight the Datapath that would be used in an ADD Immediate instructionExample: ADDI s0, s0, Imm                List and describe the stages of the classical MIPS pipeline?              Consider a 10 billion instruction program, consisting of 20% loads, 20% stores, and 60% other instructions. Will this program run faster on processor A or processor B?Processor A: A 200 MHz single cycle processor.Processor B: A 1000MHz multi-cycle processor on whichloads take 10 cycles;stores take 8 cycles; andall other instructions take 4 cycles.               How many cycles are required to run the following code on a Single cycle MIPS processor? Calculate the CPI of the program?ADDI $t1, $t1, 1ADDI $t2, $t2, 4ADDI $s0, $0, 16while:   BEQ $s0, $0, DoneADDI $s0, $s0, -1J whileDone            How many cycles are required to run the following code on a multicycle MIPS processor? Calculate the CPI of the program?ADDI $s0, $0, 5while:   BEQ $s0, $s0, DoneADDI $s0, $s0, -1J whileDone:           Please list and define the three types of pipeline hazards that exist. Also, for each of the hazards, list at least one method of reducing the number of occurrences of the hazard.                     For the code sequence below, state whether it must stall, can avoid stalls using only forwarding, or can execute without stalling or forwarding.i1: addi $t1, $t0, 1 i2: addi $t2, $t1, 2i3: addi $t3, $t0, 2 i4: addi $t4, $t0, 4 i5: addi $t4, $t3, -1 i6: beq $t0, $0, end end:Which lines in the program would require stalls based on data dependenciesReorder the program so that no stalls are required.

Accepted Answer

AS PER THE BARTLEBY POLICY I HAVE ANSWERD ONLY FIRST QUESTION

Type	Instruction Memory	Register Read	ALU Operation	Data Memory	Register Write	Total
R-Format	250	150	200	0	20	620
lw	250	150	200	250	20	870
sw	250	150	200	250	0	850
beq	250	150	200	0	0	600
J	250	0	0	0	0	250

RegDest	Jump	Branch	MemRead	MemtoReg	ALUop	MemWrite	ALUSrc	RegWrite