A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles. Thereafter, it takes 15 clock cycles to transfer each byte. The mi- croprocessor is clocked at a rate of 10 GHz. a. Determine the length of the instruction cycle for the case of a string of 64 bytes. b. What is the worst-case delay for acknowledging an interrupt if the instruction is noninterruptible? c. Repeat part (b) assuming the instruction can be interrupted at the beginning of each byte transfer.
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- Two algorithms A and B report time complexities expressed by the functions n2and 2n , respectively. They are to be executed on a machine M that consumes 10–6 s to execute an instruction. What is the time taken by the algorithms to complete their execution on machine A for an input size of 50? If another machine N that is 10 times faster than machine M is provided for the execution, what is the largest input size that can be handled by the two algorithms on machine N? What are yourobservations?Assume that a program requires the execution of 125x106 FP (floating point) instructions, 130x106 INT (integer) instructions, 150x106 L/S (load/store) instructions, and 110x106 branching instructions. These instructions have CPIs of 1, 1, 8 and 4, respectively. Assume that the processor has a 5 GHz clock rate. a. Is it possible to run the program twice as fast if we improve the CPI of just the L/S instructions? If so, by how much? Show your calculations. b. What is the Speedup in the execution time of the entire program if the CPI of INT and FP instructions is reduced by 40% and that of L/S and branching instructions is reduced by 50%?On a uniprocessor, portion A of program P consumes 24 seconds, while portion B consumes 822 seconds. On a parallel computer, moderately serial portion A speeds up 4 times, while perfectly parallel portion B speeds up by the number of processors. 1- What is the speedup of program P on 1,024 processors? _______ times 2- How many processors are required to achieve at least half the theoretical maximum possible speedup on P?
- Assume that the state of the 8088’s registers and memory just prior to the executionof each instruction in problem 15 is as follows: * in photos*What result is produced in the destination operand by executing instructions (a)through (k)? *only b,c,e,g* b) ADC SI, AX(c) INC BYTE PTR [0100H] (e) SBB DL, [0200H] (g) NEG BYTE PTR [DI]+0010HAssume that the state of the 8088’s registers and memory just prior to the executionof each instruction in problem 15 is as follows: * in photos*What result is produced in the destination operand by executing instructions (a)through (k)? *only h through k* (h) MUL DX(i) IMUL BYTE PTR [BX+SI](j) DIV BYTE PTR [SI]+0030H(k) IDIV BYTE PTR [BX][SI]+0030HConsider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?
- Let's pretend for a moment that we have a byte-addressable computer with 16-bit main memory addresses and 32-bit cache memory blocks, and that it employs two-way set associative mapping. Knowing that each block has eight bytes, please calculate the size of the offset field and provide evidence of your calculations.A certain microprocessor requires either 2, 3, 4, 8, or 12 machine cycles to perform various operations. A total of 25% of its instructions require 2 machine cycles, 20% require 3 machine cycles, 17.5% require 4 machine cycles, 12.5% require 8 machine cycles, and 25% require 12 machine cycles.Q) Suppose this system requires an extra 20 machine cycles to retrieve an operand from memory. It has to go to memory 40% of the time. What is the average number of machine cycles per instruction for this microprocessor, including its memory fetch instructions?The unique addresses assigned to the four registers (R11,R12,13,R14) of the I/O interface are equal to the XX3 , XX7 , XXB and XXF in Hex . Where XX is hex digits equal to your roll no . (if student is having roll no 45 than address are 453 ,457 ,45B , 45F in Hex ) .Show the well labeled external circuit that must be connected between and 12-bit I/O address from the CPU and the CS, RSI, and RS0 Inputs of the Interface.
- a. We are given a system with 2 levels of cache, L1 and L2. The CPU directly interfaces to the L1 cache, which has a hit time of 1 ns and a hit rate of 0.4. On misses, the L1 accesses the L2 cache, which has an access time of 20 ns, and a hit rate of 0.8. If the L2 misses, it accesses the main memory, which has an access time of 100 ns. Determine the average memory access time, of the CPU to the memory hierarchy.b. A cache is inserted between the main memory, which is 32 MB, and the CPU. This cache can accomodate 64 blocks and each block can accomodate 128 words (2B per word). How many possible blocks can be stored in one cache block if it is a direct-mapped cache?In this exercise, we examine in detail how much an instruction is executed in a single-cycle Datapath. The problem refers to a clock cycle in which the processor fetches the following instruction word: 1010 1100 0110 0010 0000 0000 0001 0100. Assume that data memory is all zeros and that the processor's registers have the following values at the beginning of the cycle in which of the instruction word is fetched: (See image attached) What is the new PC address after this instruction is executed? Highlight the path through which this value is determined?Suppose that the execution time of a given program on a single processor is 9.5 ms. If you run this program on a system having 18 independent processors, you observe an overall speedup of 1.1. Using Amdahl’s Law, what must have been the fraction of the program that could be executed in parallel? (Express the answer in decimal form, i.e., if 50% of the program can be enhanced, enter 0.5. Round to three decimal places)