A swapping system eliminates holes by compaction.Assuming a random distribution of many holes and many data segments and a time to read or write a 32 bit memory word of 14 uses about how long does it take to compact 4 GB. For simplicity assume that word O is part of a hole and that the highest word in memory contains valid data
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A swapping system eliminates holes by compaction.Assuming a random distribution of many holes and many data segments and a time to read or write a 32 bit memory word of 14 uses about how long does it take to compact 4 GB. For simplicity assume that word O is part of a hole and that the highest word in memory contains valid data
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- Let's pretend for a moment that we have a byte-addressable computer with 16-bit main memory addresses and 32-bit cache memory blocks, and that it employs two-way set associative mapping. Knowing that each block has eight bytes, please calculate the size of the offset field and provide evidence of your calculations.Create a memory mapping from the cache memory of 512 MB to the main memory of 4 GB using the four-way set associative approach with a block size of 1 MB. Consider that each memory location may be accessed using a byte address.Let's pretend for a moment that we have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. The following holds true if each block is 16 bits in size:a) Determine how many bytes the offset field is.Measure the tag field's width and height in pixels (b).
- Q3 Consider a swapping system in which main memory contains the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive segment requests of (a) 12K, (b) 10K and (c) 9K for Next-Fit? Assume the last allocated hole is 20K.Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?please no chatgpt answer . Consider a demand-paging system with a paging disk that has an average access and transfer time of 20 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference, if the page-table entry is in the associative memory. Assume that 80 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2 percent of the total) cause page faults. What is the effective memory access time? Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6. Assuming demand paging with four frames, Show which pages are resident under the LRU, FIFO, and Optimal replacement algorithms by filling out the following tables. How many page faults would occur…
- Consider a 32-bit computer with the MIPS assembly set, that executes the following code fragment loaded in memory in the address 0x0000000. li $t0, 1000 li $t1, 0 li $t2, 0 loop: addi $t1, $t1, 1 addi $t2, $t2, 4 beq $t1, $t0, loop This computer has a 4-way associative cache memory of 32 KB and lines of 16 bytes. Calculate the number of cache miss of the previous code, and the hit ratio, assuming that no other program is executing and that the cache memory is initially empty.A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?Suppose a byte-addressable computer using set associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
- Consider a three-level memory hierarchy, M1, M2 and M3, with access times 1, 10 and 100 clock cycles, costs per byte $0.02, $0.01 and $0.001, and capacities 64K, 512K and 4G Bytes, respectively. (Note that the access times are between the CPU and corresponding memory level). The M1 and M2 hit ratios are 98%, 91%, respectively. What is the AMAT for this system? Round your answer to two decimal places.Let's pretend for a moment that we had a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 cache memory blocks at our disposal. Using the information that there are 8 bytes in each block, calculate the size of the offset field and show your results.The overhead required to read an entry in a page table (including the time to access TIB) is 60 nanoseconds. To reduce this overhead, the computer has a TIB that can hold 16 entries and be accessed in 10 nanoseconds.a) Let B = TLB lookup time, T - memory cycle time, and p = hit ratio. Finda formula that expresses the effective access time.b) What hit ratio is needed to reduce the effective access time to 70 nanoseconds?