stages (ID, RF1, RF2) cach of latency 2.2/3S. Alsa, the EX stage is spılt into two stages(EXI, EX2) cach of latency 1 ns The newdesign has a total of eight pipeline stages.A program has 20% branch instructionswhich execute in the EX stage and producethe next instruction pointer at the end of theEX stage in the old design and at the end ofthe EX2 stage in the new deign. The IF stagestalls after fetching a branch instruction untlthe next instruction pointer is computed.All instructions other than the branchinstruction have an average CPI of one inboth the designs. The execution times of thisprogram on the old and the new design are Pand Q nanoseconds, respectively. The valueof PQ is An instruction pipeline has tive stagesmely. instruction fetch (IF), instructionecode and register fetch (ID/RF), instructionocution (EX), memory access (MEM), andester writeback (WB) with stage latenciesI s 22 ns, 2 ns, I ns, and 0.75 ns,espectively (ns stands for nanoseconds). Topin in terms of frequency, the designers havedecided to split the ID RF stage into three

An instruction pipeline has five stages mely. instruction fetch (IF), instruction ecode and register fetch (IDRF), instruction ocution (EX), memory access (MEM), and epster writeback (WB) with stage latencies Is. 22 ns,2 ns, I ns, and 0.75 ns, pectively (ns stands for nanoseconds). To pin in terms of frequency, the designers have decided to split the ID RF stage into three

An instruction pipeline has five stages mely. instruction fetch (IF), instruction ecode and register fetch (IDRF), instruction ocution (EX), memory access (MEM), and epster writeback (WB) with stage latencies Is. 22 ns,2 ns, I ns, and 0.75 ns, pectively (ns stands for nanoseconds). To pin in terms of frequency, the designers have decided to split the ID RF stage into three

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Similar questions

Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles х 10^ x 10^ A х 10^ х 10^ x 10^ х 10^ C
Consider two different implementations of the same instruction set architecture.The instructions can be divided into four classes according to their CPI (classA, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 2, 3, 4, and 4, andP2 with a clock rate of 3 GHz and CPIs of 2, 2, 3, and 1. Given a program witha dynamic instruction count of 1.0E6 instructions divided into classes asfollows: 10% class A, 20% class B, 50% class C, and 20% class D, whichimplementation is faster?
Considertwodifferentimplementationsofthesameinstruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2, and 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D, which implementation is faster? a. WhatistheglobalCPIforeachimplementation?
As a result, the specific mechanisms by which an instruction obtains its input data are decoupled from the specific means by which any other instruction obtains its input data. Use with a(n): A Synthesizing data sets using procedural descriptions B In contrast to the case of "multiple data, multiple instruction," in which C D stands for "data alone," there is just a single instruction. Many outcomes from a single order
Consider two different implementations of the same instruction set architecture. The instructions can be divided into three classes according to their CPI (class A, B, C). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 30% class A, 30% class B, 40% class C, which implementation is faster? What is the global CPI for each implementation? Find the clock cycles required in both cases.
Consider a CPU that implements a single instruction fetch–decode–execute–write- back pipeline for scalar processing. The execution unit of this pipeline assumes that the execution stage requires one step. Describe, and show in diagram form, what happens when an instruction that requires one execution step follows one that requires four execution steps.
2. Suppose we have two implementations of the same instruction set architecture.Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some programand computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the sameprogram. Which computer is faster for this program and by how much?
A CPU has an instruction pipeline with the following 4 segments. 1.F1(Fetch Instruction) 2.DA(Decode, Address) 3.FO(Fetch Operand) 4.EX(Execution) D1: Add R1,R2 //R1=R1+R2 Add R4,R1 //R4=R4+R1 Add R4,R3 //R4=R4+R3 Cmp R4,R5 // compare R4 and R5 Jg D1 //if Jump Greater (if R4>R5) Sub R2,R1 //R2=R2-R1 Sub R2,R3 //R2=R2-R3 Jmp D1
The runtimes of the five stages of executing an instruction in a non-pipelined machine are listed below. Instruction Fetch 100ps Instruction Decode 200ps ALU 300ps Memory 300ps Write Back 200ps This is then converted into a pipelined machine M1 using the most critical stage as the cycle time. For a new machine M2, we are allowed to break up exactly one stage into two substages of equal times giving us a six stage pipeline. A1: Discuss in short clear sentences the latency differences between the machines M1 and M2. A2: Discuss in short clear sentences the throughput differences between the machines M1 and M2.
Consider a fairly standard 5-stage pipeline: Fetch; Decode; Execute; Memory; Writeback. Let the processor be a nice, simple RISC single-cycle machine. The instructions below are executed. The branch should be taken — however, this processor does no prediction and always assumes a fall-through. Draw a Gantt chart for this and determine the branch penalty. SUB R1, R1, #1 BEQ R1, R0, LoopDone LOAD R2, Memory(100) SUB R3, R2, R1 MUL R3, R3, R3 LOAD R4, Memory(200) ADD R5, R4, R3 STORE R5, Memory(204)
Follow this steps. Have to Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?.
If the execution time of pipeline instruction execution is not balanced, what inefficiency must be introduced to allow the piplelined execution to occur? Describe this inefficiency.