Select a choice and provide a brief explanation please Question 1: Single-cycle processor clockA processor has the following mix ofinstruction types, which requiredifferent amounts of time toWhat is the fastest clock this single-cycle processor can use?1. 1250 ps2. 800 ps3. 250 ps4. 200 pscomplete the combinational logicfor each one.InstructionTime% ofInstructionsТурe 1800ps30%Туре 2200ps20%Туре 3250ps50% Question 2: Single-cycle processors efficiencyA processor has the following mix ofinstruction types, which requiredifferent amounts of time toWhat % of the time is wastedexecuting 10 instructions?1. "80%complete the combinational logicfor each one.2. ~50%3. "20%InstructionTime% of4. "0%InstructionsТурe 1800ps30%Туре 2200ps20%Туре 3250ps50%Total time:Time wasted:% Wasted:

question 1 answer is 1 1250ps single-сyсle СРU, the minimum сlосk рeriоd is simрly the…

Answered: and provide a brief explanatio

Engineering

Computer Science

and provide a brief explanatio

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?
Assume a 3GHz processor executes three classes of instructions(A, B, C).i. Calculate the average CPI for this sequence of program.ii. Calculate the execution time for this sequence of program.iii. If we use a system with four same processors, there will bespeed up by a factor of 4 for classes A and C, but class B willremain unaffected. Calculate the new execution time for thissystem. What is the overall speed up? Class A B C CPI for class 4 2 10 IC in sequence 100 200 300
A particular (fictional) CPU has the following internal units and timings (WRand RR are write/read registers,ALU does all logic and integer operations and there is a separate floatingpoint unit FPU. Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. STORE: IR+RR+ALU+MEM : 730, 10%3. LOGIC/INTEGER: IR+RR+ALU+WR : 520, 40%4. FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. BRANCH: IR+RR+ALU : 270, 20%1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption thatall instructions take 1 cycle (assume all memory access is in cache). Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1
Assume that a personal computer must get FIVE pieces of data from itsmemory for every operation (one piece of data indicates Which instructionto perform: the other is the intormation which is operated on). If thecomputer is the size of a typical PC. how long does it take to get these pieceof data? From this, what is the maximum rate at which the PC can executeuctions?
Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3.1 GHz clock rate and a CPI (cycles per instruction) of 1.6. P2 has a 2.4 GHz clock rate and a CPI of 1.2. P3 has a 4.0 GHz clock rate and has a CPI of 2.0 If you could answer these id appreciate that greatly. a.Which processor has the highest performance expressed in instructions per second? b.If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions. c.We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?
Our favorite program runs in 10 seconds on computer A, which has a 2 GHz clock. We are trying to help a computer designer build a computer, B, which will run this program in 6 seconds. Th e designer has determined that a substantial increase in the clock rate is possible, but this increase will affect the rest of the CPU design, causing computer B to require 1.2 times as many clock cycles as computer A for this program. What clock rate should we tell the designer to target?
Question: Suppose a program of 600 instructions runs on a 2 GHz processor. The frequency of instructions and the clock cycle counts per instruction are given as follows. What is the average CPI of this instruction mix? Operation Frequency Clock Cycles ALU operations 55% 1 Loads/Stores 30% 2 Branches 15% 3 Question: Continue from the previous question. What is the CPU time of the program in nanoseconds? Question: Suppose a processor P has a 2.5 GHz clock rate and a CPI of 1.5. If the processor executes a program in 3 microseconds, find the number of instructions in the program.
Assume a program requires the execution of 75 ×106 FP instructions, 112 ×106INT instructions, 88 ×106 L/S instructions, and 12 × 106 branch instructions.The CPI for each type of instruction is 1, 3, 4, and 2, respectively. Assume thatthe processor has a 2 GHz clock rate.a) By how much must we improve the CPI of FP instructions if we wantthe program to run two times faster?b) By how much must we improve the CPI of L/S instructions if we wantthe program to run two times faster?c) By how much is the execution time of the program improved if theCPI of INT and FP instructions is reduced by 40% and the CPI of L/Sand Branch is reduced by 30%?
Q1. Professor Mikka Singh of Harvard University has proposed a new atomic instruction named “Gurru”. The atomic instruction will work exactly like Semaphores except it will take 2 clock cycles to execute. He proposed that a on a multi-processor environment while the instruction Gurru will be executing on any one of the processor then all the other processors shall be halted. However, the Operating System Lab Engineers at Harvard are still confused about whether the newly proposed instruction will work or not. What are your thoughts?
3. The table below shows instruction-type breakdown for different programs. Using this data, you will be exploring the performance trade-offs for different changes made to an MIPS processor. Compute Load Store Branch Total Program1 600 600 200 50 ? Program2 900 500 100 200 ? a. Assuming that computes take 1 cycle, loads and store instructions take 10 cycles, and branches take 3 cycles, find the execution time for both the programs on a 3 GHz Processor. b. Assuming that computes take 1 cycle, loads and store instructions take 2 cycles, and branches take 3 cycles, what is the speedup if the number of compute instruction can be reduced by one-half?
The table below shows instruction-type breakdown for different programs. Using this data, you will be exploring the performance trade-offs for different changes made to an MIPS processor. Class A Class B Class C Class D Total Program1 90 100 30 10 ? Program2 110 70 20 20 ? Calculate the total instructions required by each of the programs. Assuming that Class A take 1 cycle (CPI) , B and C instructions take 2 cycles, and D take 3 cycles, find the execution time for both the programs on a 3 GHz Processor. What is the speedup if the number of A instruction can be reduced by half and D instructions increased to double? (for both the programs)