Answer the following questions. Clearly show your work. (a) Figure Q.4.1 shows a negative edge triggered T and JK flip-flops connected in series. Assume the outputs of all flip-flops are initially zero (i.e. A = B = 0), TM complete the timing diagram in Figure Q.4.2 for A and B. TM TM & UT

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5Fioure 0.4.3
A and B.
complete the timing diagram in Figure Q.4.2 f
Q.4 Answer the following questions. Clearly show your work.
(a) Figure Q.4.1 shows a negative edge triggered T and JK flip-flops connected in
series, Assume the outputs of all flip-flops are initially zerö (i.e. A = B = 0),
5 UTM 8 UTM
5 UTM 8 UTM UTM
S UTM
5 UTM 5 UT
UTM
J
5 UTM 8 UTM 5 UTM
B
UT
ck
5 UT UTM
K
5 UTM 5 UT
8 UTM 5 UTM & UTM
UTM
Figure Q.4.1
clk
3 UTM 5 UT
8 UTM 8 UTM UTM
5 UTM
A
8 UTM 5 UT
5 UTM & UTM 8 UTM
5 UTM
5 UTM
8 UTM
5 UTM 5 UT
Figure Q.4.2 UTM
5 UTM
M 8 UTM
and basic gates. The counter should change state at every negative edge of the
8 UTM & UT
UTM
Q.4.3 using D flip-flops
5 UTM 5 UTM 5 U
M& UTM
3 UTM 8 UT
6 UTM 5 UTM 8 UTM
8N TM 8 UTM
111
5 UTM 5 UT
ITM 5 UTM
101
5 UTM 8 UTM
TITM
8 UTM 5 UT
UTM 5 UTM
Transcribed Image Text:5Fioure 0.4.3 A and B. complete the timing diagram in Figure Q.4.2 f Q.4 Answer the following questions. Clearly show your work. (a) Figure Q.4.1 shows a negative edge triggered T and JK flip-flops connected in series, Assume the outputs of all flip-flops are initially zerö (i.e. A = B = 0), 5 UTM 8 UTM 5 UTM 8 UTM UTM S UTM 5 UTM 5 UT UTM J 5 UTM 8 UTM 5 UTM B UT ck 5 UT UTM K 5 UTM 5 UT 8 UTM 5 UTM & UTM UTM Figure Q.4.1 clk 3 UTM 5 UT 8 UTM 8 UTM UTM 5 UTM A 8 UTM 5 UT 5 UTM & UTM 8 UTM 5 UTM 5 UTM 8 UTM 5 UTM 5 UT Figure Q.4.2 UTM 5 UTM M 8 UTM and basic gates. The counter should change state at every negative edge of the 8 UTM & UT UTM Q.4.3 using D flip-flops 5 UTM 5 UTM 5 U M& UTM 3 UTM 8 UT 6 UTM 5 UTM 8 UTM 8N TM 8 UTM 111 5 UTM 5 UT ITM 5 UTM 101 5 UTM 8 UTM TITM 8 UTM 5 UT UTM 5 UTM
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