Assume the CPU has access to two types of memory. Level 1 has 1000 data words and has an access time of 2.5 nanoseconds (2.5E-9 sec) between the CPU and L1; level 2 contains 100,000 data words and has an access time of 5.0 nanoseconds between L1 and L2 transfers (5.0E-9 sec) Assume that the CPU's data requests have a hit ratio, H, of 0.7 in the L1 cascade, and that any requests missed in L! are assured to be found in L2. What is the average memory assessment time in nanoseconds for CPU data requests?

Assume the CPU has access to two types of memory. Level 1 has 1000 data words and has an access time of 2.5 nanoseconds (2.5E-9 sec) between the CPU and L1; level 2 contains 100,000 data words and has an access time of 5.0 nanoseconds between L1 and L2 transfers (5.0E-9 sec) Assume that the CPU's data requests have a hit ratio, H, of 0.7 in the L1 cascade, and that any requests missed in L! are assured to be found in L2. What is the average memory assessment time in nanoseconds for CPU data requests?

Name: Assume the CPU has access to two types of memory.Level 1 has 1000 data
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Description: Assume the CPU has access to two types of memory.Level 1 has 1000 data words and has an access time of 2.5 nanoseconds (2.5E-9 sec) between the CPU and L1; level 2 contains 100,000 data words and has an access time of 5.0 nanoseconds between L1 and L

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Suppose that the processor has access to two levels of memory. Level 1 contains 1000 data words and has an access time between the CPU and L1 of 2.5 nanoseconds (2.5E-9 sec); level 2 contains data 100,000 words and has an access time between L1 and L2 transfers of 5.0 nanoseconds (5.0E-9 sec) Assume that data requests by the CPU have a hit ratio, H in the L1 cascade of 0.7, and any requests missed in L! Are guaranteed to be found in L2. What is the average memory assess time in nanoseconds for data requests by the CPU?
Suppose that the processor has access to two levels of memory. Level 1 contains 1000 data words and has an access time between the CPU and L1 of 2.5 nanoseconds (2.5E-9 sec); level 2 contains data 100,000 words and has an access time between L1 and L2 transfers of 5.0 nanoseconds (5.0E-9 sec). What is the average memory assess time in nanoseconds for data requests by the CPU?
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Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM). The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́ 10-9 secs). (a) What is the overall memory access time given a cache hit rate of 95%? (b) What will the cache hit rate need to be if the overall memory access time in (a) is to be halved?
Suppose a given processor has access to two levels of memory. Level 1 contains 1000 words and has an access time of 0.01 μs; level 2 contains 100,000 words and has an access time of 0.1 μs. Assume that if a word to be accessed is in level 1, then the processor accesses it directly. If it is in level 2, then the word is first transferred to level 1 and then accessed by the processor. For simplicity, ignore the time required for the processor to determine whether the word is in level 1 or level 2. Suppose 95% of the memory accesses are found in level 1, define the hit ratio (H) and find the average access time.
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5. Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. (a) Suppose all instructions and operands are one byte long, by what factor do the maximum data transfer rates differ?