Assume the following values are stored at the indicated memory addresses, and registers: Address Value Register Value 0x1100 OxBB 0x1100 0x1101 0x00 0x1 0x1102 0x00 0x2 0x1103 0x00 0x4 0x1104 OXEE 0x1105 0x00 0x1106 0x00 0x1107 0x00 0x1108 OxAA 0x1109 0x00 0x110A 0x00 0x110B 0x00 0x110C OxDD 0x110D 0x00 0x110E 0x00 0x110F 0x00 %rdi %rsi %rdx %rcx Fill in the following table showing the effects of the following instructions, in terms of both the register or memory location that will be updated and the resulting value: Assume that the instructions are part of a program, and that they are executed sequentially from top to bottom. Destination Value in Hexadecimal Instruction addq %rsi, 4(%rdi, %rdx, 2) incq %rsi decq %rdx negq %rcx andq %rdi, %rcx addq (%rdi). %rsi leaq 4356(, %rdx, 8), %rsi xorq 2(%rdi, %rdx, 4), %rcx movswq (%rsi). %rdi leaq 4(%rsi, %rdi, 2), %rcx

Assume the following values are stored at the indicated memory addresses, and registers: Address Value Register Value 0x1100 OxBB 0x1100 0x1101 0x00 0x1 0x1102 0x00 0x2 0x1103 0x00 0x4 0x1104 OXEE 0x1105 0x00 0x1106 0x00 0x1107 0x00 0x1108 OxAA 0x1109 0x00 0x110A 0x00 0x110B 0x00 0x110C OxDD 0x110D 0x00 0x110E 0x00 0x110F 0x00 %rdi %rsi %rdx %rcx Fill in the following table showing the effects of the following instructions, in terms of both the register or memory location that will be updated and the resulting value: Assume that the instructions are part of a program, and that they are executed sequentially from top to bottom. Destination Value in Hexadecimal Instruction addq %rsi, 4(%rdi, %rdx, 2) incq %rsi decq %rdx negq %rcx andq %rdi, %rcx addq (%rdi). %rsi leaq 4356(, %rdx, 8), %rsi xorq 2(%rdi, %rdx, 4), %rcx movswq (%rsi). %rdi leaq 4(%rsi, %rdi, 2), %rcx

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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A(n) __________ is a storage location implemented in the CPU.
If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
Suppose r0 = ox300010A0, r2 = 0x00000011, and the memory layout is as follows Address: Data: 0x300010A7 0x72 0x300010A6 0XA5 0x300010A5 0x9F 0x300010A4 0x00 0x300010A3 0x50 0x300010A2 0x2B 0x300010A1 0XA5 0x300010A0 0x01 -What is the Value of r0 and r1 after executing LDR r1, [r0, #2] -What are the values of r0 and r1 after executing the following code? Illustrate your process in a memory map. LDR r1, [r0], #3 ADD r1, r1, r2 STR r1, [r0, r#4]
Suppose r0 = ox300010A0, r2 = 0x00000011, and the memory layout is as follows Address: Data: 0x300010A7 0x72 0x300010A6 0XA5 0x300010A5 0x9F 0x300010A4 0x00 0x300010A3 0x50 0x300010A2 0x2B 0x300010A1 0XA5 0x300010A0 0x01 -What are the values of r0 and r1 after executing the following code? Illustrate your process in a memory map. LDR r1, [r0], #3 ADD r1, r1, r2 STR r1, [r0, r#4]
Assume the following values are stored at the indicated memory addresses and registers Address Value 0x100 0xaaa 0x104 0x123 0x108 0x12 0x10c 0x10 Register Value %eax 0x100 %ecx 0x1 %edx 0x3 Fill up the following table: %eax 0x104 $0x108 (%eax) 4(%eax) 9(%eax,%edx) 260(%ecx,%edx) 0xFC(,%ecx,4) (%eax,%edx,4)
Assume the following values are stored at the indicated memory addresses and registers:Address Value Register Value0x200 0xFF %rax 0x2000x204 0xAA %rcx 0x10x208 0x11 %rdx 0x30x20C 0x13Fill in the following table showing the values for the indicated operands: Operand Valueaddq %rcx,(%rax) ------------------subq %rdx,4(%rax) -------------------imulq $16, (%rax,%rdx,4) --------------------incq 8(%rax) -------------------decq %rcx -------------------subq %rdx,%rax ---------------------xorq %rdx,%rdx --------------------sarq 3, %rdx --------------------notq %rdx -------------------
What memory address (0 through 256) is represented by each of the following hexadecimal numbers: (a) 0A16 (b) 3F16 (c) CD16
1. Assume the memory uses big endian addressing, find the byte stored in 0x20000001 if the address of the memory 0x20000000 contains the value 0x89346710. 2. Assume the memory uses little endian addressing, find the value of r0 after the instruction LDRSB r0, [#0x20000000] if the address of the memory 0x20000000 contains the value 0x893467B0.
Q5. Given the content of memory and the registers below. i. Indicate the type of addressing mode of each line of instruction belowii. Deduce the target addressiii. Deduce the Value loaded into accumulator register (A) 10 marks Data at location Memory Address03600 3030103000 360000C303 6390003030 C303Memory content Base Register (B) 00600Program Counter (Pc) 003000Index Register (X) 000090 Register Content Instructions Opcodes - LDA = 00SN opcode n i x b p e Displacement Target Address (TA)1 000000 1 1 0 0 1 0 0110 0000 0000 2 000000 1 1 1 1 0 0 0011 0000 0000 3 000000 1 0 0 0 1 0 0000 0011 0000 4 000000 0 1 0 0 0 0 0000 0011 0000 5 000000 1 1 0 0 0 1 0000 1100 0011 0000 0011
the available space list of a computer memory is specified as follows: 9 start address block address in words 100 50 200 150 450 600 1200 400 determine the available space list after allocating the space for the stream of requests consisting of the following block sizes: 25,100,250,200,100,150 use i) first fit ii) best fit and iii) worst fit algorithms
The 32-bit number 52AB43FC (in hexadecimal) is stored in abyte-addressable memory starting at physical address FE08 (in hex) using Little-Endian notation. The byte(value ni hexadecimal) stored at theaddress FE0B will be
Assume a computer that has 32-bit integers. Use a table to clearly show how each of the following values would be stored sequentially in memory, starting at address 0x100, assuming each address holds one byte. 0x123456BA 0xabcde -28 (decimal values, assume the machine uses 2's complement notation. 0xFEDC