Assume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 5%. If a processor has a CPI of 3 without any memory stalls, and the miss penalty is 50 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 44%
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Assume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 5%. If a processor has a CPI of 3 without any memory stalls, and the miss penalty is 50 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 44%.
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- Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?Consider a two-level memory system (i.e., cache and main memory). Assume the cache access time is 3 clock cycles, and the hit rate is 95%. What should be the main memory access time (penalty) to ensure the memory access efficiency stays at 0.90?
- If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?Assume we have a computer where the clocks per instruction is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores and these total 50% of the instructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, how much faster would the computer be if all instructions were cache hits?Suppose a 1 MiB L1 cache has an access time of 1 clock cycle, the 16 MiB L2 has an access time of 4 clock cycles, and the 8 GiB DRAM has an average access time of 40 clock cycles. 80% of memory reads are satisfied by the L1 cache. Only 10% have to go to main memory. (a) What is the AMAT following a miss on L1? (b) What is the AMAT for memory overall?
- Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?Suppose we have a processor with a base CPI of 1, assuming all references hit in the primary cache, and a clock rate of 2 GHz. Assume a main memory access time of 200 ns, including all miss handling. Suppose the miss rate per instruction at the primary cache is 3%. How much faster will the processor be if we add a secondary cache that has 10 ns access time for either a hit or a miss and is large enough to reduce the miss rate to main memory to 1%?Suppose you have a processor with a base CPI of 1.0, and two caches (L1 and L2). You have the following specifications Clock rate= 5 GHz. Access time to L2 Cache = 6 ns Access time to Main memory = 100 ns Miss rate per instruction at the L1 cache is 2.5%. Miss rate per instruction at the L2 cache is 0.7%. A program contains 3000 instructions, 600 of them are memory access instructions. Taking into consideration the stalls on Data cache only, find the total average CPI. a.2.63 b.None of them c.1.16 d.1.45 e.2.13
- Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM). The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́ 10-9 secs). (a) What is the overall memory access time given a cache hit rate of 95%? (b) What will the cache hit rate need to be if the overall memory access time in (a) is to be halved?Suppose you have a processor with a base CPI 1.0, assuming all references hit in theprimary cache (L1), and a clock rate of 3 GHz. Assume that you have two caches (L1and L2). L2 cache access time is 10 ns and main memory access time is 200 ns,including all the miss handling. Suppose the miss rate per instruction at the L1 cache is10%, L2 cache is 5%.a) What is the effective CPI?b) What will be the effective CPI if we add a new cache (L3) that has 50 nsaccess time and reduce the miss rate to main memory to 1%?You are asked to perform capacity planning for a two-level memory system. The first level, M1 is a cache with three capacity choices of 64Kbytes, 128Kbytes, and 256Kbytes. The second level, M2, is a main memory with a 4Mbyte capacity. Let c1 and c2 be the costs per byte and t1 and t2 be the access times for M1 and M2, respectively. Assume c1 = 20 * c2 and t2 = 10 * t1. The cache hit ratios for the 3 capacities are assumed to be 0.7, 0.9 and 0.95, respectively. What is the average memory access time, AMAT, if t1 = 20ns in the three cache designs? (Note that t1 is the time from M1 to CPU and t2 is that from M2 to CPU. This means that t2 includes t1).