PC Read address Add Instruction Instruction memory Read register 1 Read register 2 Registers Read data 2 Write register Write data RegWrite Read data 1 16 Sign- extend 32 Shift left 2 ALUSrc E3X Add ALU result ALU operation Zero ALU ALU PCSrc result Address MemWrite MemRead Read data Write Data data memory MemtoReg MUX
PC Read address Add Instruction Instruction memory Read register 1 Read register 2 Registers Read data 2 Write register Write data RegWrite Read data 1 16 Sign- extend 32 Shift left 2 ALUSrc E3X Add ALU result ALU operation Zero ALU ALU PCSrc result Address MemWrite MemRead Read data Write Data data memory MemtoReg MUX
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Your Question:
Assume that individual stages of the datapath have the following latencies:
- IF: 250ps
- ID: 350ps
- EX: 150ps
- MEM: 300ps
- WB: 200ps
-
- List the required stages for each of the following types of instructions: load, store, r-type, branch.
- What is the execution time of each type of instruction assuming only the required stages execute for each instruction?
- Assuming the same instruction mix listed in Problem 7, what is the average execution time across all instructions?
- Assuming pipelining is used, what would be the necessary clock cycle time?
- Assuming pipelining is used, what would be the execution time for a single load instruction to execute?
- Use the average instruction execution time calculated in Part d of this problem to determine the overall speed-up gained by pipelining. Assume the processor continuously runs with a full pipeline and hazards are completely avoided.
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