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- Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least___(bits)?.We have a computer with a Direct Mapped Memory Cache. The main memory is 16GB and the cache is 64KB. The size of a block is 512B. Explain what a Direct Mapped Memory Cache is and how it works in this particular example.
- If a 2 GHz processor graduates an instruction every third cycle, how many instructions are there in a program that runs for 10 seconds?The connection between the central processing unit and the memory might be a synchronous or an asynchronous bus. Which one is more nimble and quick? Please detail your reasoning process.The 20-bit address bus has a memory addressing capability of 20 megabytes. microcontroller?
- CPU and memory connections should be made over a synchronous or asynchronous bus. Which one has the edge in terms of acceleration and dexterity? Step by step instructions on how you came up with the outcome you did.The length of a computer instruction is 10 bits, and the size of an address field is 3 bits. FIFTEEN 2-address instructions and SEVEN 1-address instructions have already been created by the system architect. How many 0-address instructions can the instruction set architecture support?A computer has 512 MB (megabytes) of memory. Assum the memory is byte addressable, how many bits are needed to address each loaction?
