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- How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?Assume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 5%. If a processor has a CPI of 3 without any memory stalls, and the miss penalty is 50 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 44%.
- Assume we have a computer where the clocks per instruction is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores and these total 50% of the instructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, how much faster would the computer be if all instructions were cache hits?If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?Assume that we are having a computer with the following characteristics: 1MB of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 KB. For the main memory addresses of FF010, the corresponding set number for a four-way set associative cache will be?
- Suppose that a program when it executes in a CPU it achieves average CPI=1. Suppose that 40% of the instructions of the program are causing data accesses out of which 5% are cache misses. Each cache miss has 100 cycles delay. What is the CPI for the program when considering the cache misses? • 1 • 4 • 2 • 33. Assume you have a computer where the cycles per Instruction(CPI) is 1 when all the memory accesses hit in the cache. The only data accesses are loads and stores and these total 25% of the instructions.If the miss penalty is 50 clock cycles and the miss rate is 1%, how much faster would the computer if all the instructions were cache hits?What are the two main steps involved in an instruction cycle? If the CPU needs to be alerted by the keyboard and the mouse at the same time, How the CPU will handle interrupts from the keyboard and the mouse at the same time? There are two ways... Which cache mapping does not need a replacement algorithm? Which cache mapping scheme has the largest TAG? Only a microprocessor is accessing the memory via cache i.e. no other device is reading from memory. Which cache write the policy will you use and why.
- Show work and type answer please. Suppose a computer using fully associate cache has 2G Bytes of main memory and a cache of 256 Blocks, where each cache Block has 8 Words, and the Word Size is 2 Bytes. a. How many blocks of main memory? b. What is the format of a memory address as seen by the cache? c. To which cache block will the memory reference 00001C4A in Hex?. Consider a system that has multiple processors where eachprocessor has its own cache, but main memory is shared among allprocessors.1. a) Which cache write policy would you use?2. b) The cache coherency problem. With regard to the systemjust described, what problems are caused if a processor has acopy of memory block A in its cache and a second processor,also having a copy of A in its cache, then updates mainmemory block A? Can you think of a way (perhaps morethan one) of preventing this situation, or lessening itseffects?Because volatile RAM (Random Access Memory) already exists, what's the point of using a slower, less reliable cache memory instead?The electrical components called transistors are used in both random access memory (RAM) and cache memory. To what extent, if at all, can a computer get by with using just one kind of memory to carry out all of its functions?