Briefly discuss the importance of A/D and D/A converters for the case of digital control. Also, draw a detailed block diagram to show where a digital computer can be placed in the control loop. Q4 (a)

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Briefly discuss the importance of A/D and D/A converters for the case of digital
control. Also, draw a detailed block diagram to show where a digital computer
can be placed in the control loop.
Q4
(а)
(b)
Consider the open-loop system as shown in Figure Q4.
T.
Y(s)
ZOH
G,(s)
R(s)
U(s)
Figure Q4
The plant is described as:
* = (, -)x + ()u
y = [1 0]x
(i)
Find the transfer function of the plant, Gp(s). Note, that the transfer
function Y(s) can be defined as,
Y(s) = C(sl – A)~'B + D
where A, B, C, D and I are state, input, output, feedforward and
identity matrix respectively.
(ii)
Find the sampled-data transfer function G(z). Assume a sample
period of T, and the transfer function of the ZOH as (1-eTs)/s. [
Continued overleaf
Page 4 of 5
(iii)
Find the sampled-data transfer function, G(z), for T= 0.5 s.
(iv)
Explain why it is not practical to make sample time too low to
reduce the effective delay of sample and hold. Note, that the
effective delay of sample and hold is typically half of the sampl
time.
Transcribed Image Text:Briefly discuss the importance of A/D and D/A converters for the case of digital control. Also, draw a detailed block diagram to show where a digital computer can be placed in the control loop. Q4 (а) (b) Consider the open-loop system as shown in Figure Q4. T. Y(s) ZOH G,(s) R(s) U(s) Figure Q4 The plant is described as: * = (, -)x + ()u y = [1 0]x (i) Find the transfer function of the plant, Gp(s). Note, that the transfer function Y(s) can be defined as, Y(s) = C(sl – A)~'B + D where A, B, C, D and I are state, input, output, feedforward and identity matrix respectively. (ii) Find the sampled-data transfer function G(z). Assume a sample period of T, and the transfer function of the ZOH as (1-eTs)/s. [ Continued overleaf Page 4 of 5 (iii) Find the sampled-data transfer function, G(z), for T= 0.5 s. (iv) Explain why it is not practical to make sample time too low to reduce the effective delay of sample and hold. Note, that the effective delay of sample and hold is typically half of the sampl time.
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