Consider a hypothetical machine with the following characteristics: a. instruction format : (total of 12 bits, LSB is bit 0, MSB is bit 11) Opcode (4 bits) Address ( 8 bits) b. internal CPU registers: PC (Program Counter) – holds the address of the instruction IR (Instruction register) – holds the instruction to be executed A- temporary storage (8 bits) B- temporary storage (8 þits) c. partial list of opcodes M- memory address 0000 – STA M- store A to memory M 0001 – LDA M– load A from memory M 0011– STB M – store B to memory M 0101 – LDB M - load B from memory M 1000 – ADDA M– add data in M to A 1010 – ADDAB – add B to A Questions: 1. What is the maximum directly addressable memory locations? llanswer should be in decimal 2. What is the address range? l/format of answer : XXXX-XXXX where X is a hex digit 3. What is the size of PC? (express answer in terms of bits) 4. What is the size of IR? (express answer in terms of nibbles) 5. What is the maximum number of instructions?

Consider a hypothetical machine with the following characteristics: a. instruction format : (total of 12 bits, LSB is bit 0, MSB is bit 11) Opcode (4 bits) Address ( 8 bits) b. internal CPU registers: PC (Program Counter) – holds the address of the instruction IR (Instruction register) – holds the instruction to be executed A- temporary storage (8 bits) B- temporary storage (8 þits) c. partial list of opcodes M- memory address 0000 – STA M- store A to memory M 0001 – LDA M– load A from memory M 0011– STB M – store B to memory M 0101 – LDB M - load B from memory M 1000 – ADDA M– add data in M to A 1010 – ADDAB – add B to A Questions: 1. What is the maximum directly addressable memory locations? llanswer should be in decimal 2. What is the address range? l/format of answer : XXXX-XXXX where X is a hex digit 3. What is the size of PC? (express answer in terms of bits) 4. What is the size of IR? (express answer in terms of nibbles) 5. What is the maximum number of instructions?

Name: Question 5Consider a hypothetical machine with the following characte
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: Question 5Consider a hypothetical machine with the following characteristics:a. instruction format : (total of 12 bits, LSB is bit 0, MSB is bit 11)Opcode (4 bits)Address ( 8 bits)b. internal CPU registers:PC (Program Counter) – holds the address of

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?
Iwill all steps for The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=700 W=870 T1=100 T2=200 T3=300
Question P .Implement and Compute the total memory traffic in bytes for both instruction fetch and instruction execution for the code that implements the expression a=(b*c) d on 3-, 2-, 1-, and 0- address machines. Assume opcode occupy one byte, address occupy two bytes and data values also occupy two bytes. The word length is one byte. Full explain this question and text typing work only We should answer our question within 2 hours takes more time then we will reduce Rating Dont ignore this line
I want all steps for Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “6” addressing modes, and it has “16” computer registers. The computer supports instructions, where each instruction consists of following fields: • Mode • Operation code • Register • Register • Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
3. Assume you have a computer where the cycles per Instruction(CPI) is 1 when all the memory accesses hit in the cache. The only data accesses are loads and stores and these total 25% of the instructions.If the miss penalty is 50 clock cycles and the miss rate is 1%, how much faster would the computer if all the instructions were cache hits?
Answer the given question with a proper explanation and step-by-step solution. This question is based on the EASY68K simulated processor. Assume the contents of all data and address registers are equal to zero before the start of the program. All numbers are in hexadecimal. Demonstrate how instructions of a program are executed by using the E114 Processor Instruction Set of the EASY68K simulator. The figure above is an incomplete program to add up the first 6 data items ($1 to $6) stored at address label DATA and store the sum of the first 6 data items to address label SUM1. Finish the program to accomplish the task.
Question 15 kk .Consider a microprocessor system where the processor has a 16-bit data bus and a 20-bit address bus. Determine (in bytes) the maximum size of the bit-addressable memory that can be connected to this processor. In continuation to the previous exercise, now consider a byte-addressable memory with a 32-bit address bus. What is the maximum memory size (in bytes) that can be accessed? Full explain this question and text typing work only We should answer our question within 2 hours takes more time then we will reduce Rating Dont ignore this line
Q 1. Answer the following short questions. Support your answers with diagram, where needed: How much memory space is addressable (in bytes) by a microprocessor, if it uses 36 address lines? If Base address = A000H, Physical address = A0345H, then the offset add = ___________? Why address bus is unidirectional and data bus is bidirectional in 8086?
Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “8” addressing modes, and it has “50” computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
14.3 There exists processor with 16-bit word length (8-bit addressing unit) with a memory size of 32k words. The addressing method is register - based and direct. Instructions are encoded in two types: single-word and two-word with 3 addresses. Assuming there are no more than 576 -25- different instructions, what is the maximum possible number of general purpose registers in this processor? Note: In single-word instructions all three operands are registers
Can u please solve step by step ; clearly. Write the basic addressing modes of a CPU, and explain each one giving a simple instruction example.
Assume we have a computer where the clocks per instruction is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores and these total 50% of the instructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, how much faster would the computer be if all instructions were cache hits?